PCA8550 Datasheet, PDF (1/8 Pages) NXP Semiconductors – 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM

D EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D Useful for Jumperless Configuration of PC
Motherboard
D Inputs Accept Voltages to 5.5 V
D MUX OUT Signals are 2.5-V Outputs
D NON-MUXED OUT Signal is a 3.3-V Output
D Minimum of 1000 Write Cycles
D Minimum of 10 Years Data Retention
D Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
PCA8550
NONVOLATILE 5-BIT REGISTER
WITH I²C INTERFACE
SCPS050A – MARCH 1999 – REVISED APRIL 1999
D, DB, OR PW PACKAGE
(TOP VIEW)
I²C SCL ₁
I²C SDA 2
OVERRIDE 3
MUX IN A 4
MUX IN B 5
MUX IN C 6
MUX IN D 7
GND 8
16 ^V_CC
15 WP
14 NON-MUXED OUT
13 MUX SELECT
12 MUX OUT A
11 MUX OUT B
10 MUX OUT C
9 MUX OUT D
description
This 4-bit 1-of-2 multiplexer with I²C input interface is designed for 3-V to 3.6-V V_CC operation.
The PCA8550 is designed to multiplex four bits of data from parallel inputs or from I²C input data stored in a
nonvolatile register. An additional bit of register output also is provided, which is latched to prevent changes in
the output value during the write cycle. The factory default for the contents of the register is all low. These stored
values can be read from, or written to, using the I²C bus. The ability to control writing to the register is provided
by the write protect (WP) input. The override (OVERRIDE) input forces all the register outputs to a low.
This device provides a fast-mode (400 kbit/s) or standard-mode (100 kbit/s) I²C serial interface for data input
and output. The implementation is as a slave. The device address is specified in the I²C interface definition table.
Both of the I²C Schmitt-trigger inputs (SCL and SDA) provide integrated pullup resistors and are 5-V tolerant.
The PCA8550 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
MUX SELECT OVERRIDE
MUX OUT
NON-MUXED
OUT
L
L
L
L
L
H
Nonvolatile
register
Nonvolatile
register
Latched
H
X
MUX IN
NON-MUXED
OUT†
† _{The latched NON-MUXED OUT state is the value present on the}
NON-MUXED OUT output at the time the MUX SELECT input
transitions from the low to the high state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
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