ISO721M-EP Datasheet, PDF (1/24 Pages) Texas Instruments – 3.3-V/5-V HIGH-SPEED DIGITAL ISOLATORS

ISO721M-EP
www.ti.com....................................................................................................................................................................................................... SLLS882 – JUNE 2008
3.3-V/5-V HIGH-SPEED DIGITAL ISOLATORS
FEATURES
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•23 Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site
• Extended Temperature Performance of
–55°C to 125°C
• Enhanced Diminishing Manufacturing Sources
(DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree ⁽¹⁾
• 4000-V_(peak) Isolation
– UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2)
IEC 61010-1
– 50-kV/µs Transient Immunity Typical
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
• Signaling Rate 0 Mbps to 150 Mbps
– Low Propagation Delay
– Low Pulse Skew (Pulse-Width Distortion)
• Low-Power Sleep Mode
• High Electromagnetic Immunity
• Low Input Current Requirement
• Failsafe Output
• Drop-In Replacement for Most Opto and
Magnetic Isolators
APPLICATIONS
• Industrial Fieldbus
– Modbus
– Profibus
– DeviceNet™ Data Buses
– Smart Distributed Systems (SDS™)
• Computer Peripheral Interface
• Servo Control Interface
• Data Acquisition
DESCRIPTION/ORDER INFORMATION
The ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated
by a silicon oxide (SiO₂) insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in
conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits
from entering the local ground, and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or
resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure
the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 µs, the input is assumed
to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SDS is a trademark of Honeywell.
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DeviceNet is a trademark of Open Devicenet Vendors Association, Inc.
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UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated