DLP5500 Datasheet, PDF (1/27 Pages) Texas Instruments – DLP® 0.55 XGA Series 450 DMD

DLP5500
www.ti.com
DLP^® 0.55 XGA Series 450 DMD
Check for Samples: DLP5500
DLPS013A – APRIL 2010 – REVISED JUNE 2010
FEATURES
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• 0.55-Inch Micromirror Array Diagonal
– 1024 × 768 Array of Aluminum,
Micrometer-Sized Mirrors
(XGA Resolution )
– 10.8-µm Micromirror Pitch
– ±12° Micromirror Tilt Angle
(Relative to Flat State)
– Designed for Corner Illumination
• Designed for Use With Broadband Visible
Light (420 nm–700 nm):
– Window Transmission 97% (Single Pass,
Through Two Window Surfaces)
– Micromirror Reflectivity 88%
– Array Diffraction Efficiency 86%
– Array Fill Factor 92%
• 16-Bit, Low Voltage Differential Signaling
(LVDS) Double Data Rate (DDR) input data bus
• 200 MHz Input Data Clock Rate
• Series 450 Package Characteristics:
– Thermal Area 18.0 mm by 12.0 mm
enabling high on screen lumens (>2000 lm)
– 149 Micro Pin Grid Array
Robust electrical connection
APPLICATIONS
• 3D Machine Vision
• 3D Optical Measurement
• Industrial and Medical Imaging
• Medical Instrumentation
• Digital Exposure systems
DESCRIPTION
The DLP5500 Digital Micromirror Device (DMD) is a digitally controlled MOEMS (micro-opto-electromechanical
system) spatial light modulator (SLM). When coupled to an appropriate optical system, the DLP5500 can be used
to modulate the amplitude, direction, and/or phase of incoming (illumination) light.
Architecturally, the DLP5500 is a latchable, electrical-in/optical-out semiconductor device. This architecture
makes the DLP5500 well suited for use in applications such as structured lighting, 3D optical metrology,
Industrial & Medical imaging, microscopy, and spectroscopy. The compact physical size of the DLP5500 enables
integration into portable equipment.
The DLP5500 is one of three components in the DLP 0.55 XGA chip-set (see Figure 1). Proper function and
operation of the DLP5500 requires that it be used in conjunction with the other components of the chip-set. The
DLPC200 (TI literature number DLPS014) and DLPA200 (TI literature number DLPS015) control and coordinate
the data loading and micromirror switching to guarantee reliable operation. Refer to DLP 0.55 XGA chip-set data
sheet (TI literature number DLPZ004) for further details. DLPR200F is DLPC200 firmware code provided to
enable Video and Structured Lighting Applicaions. To locate the latest version of the DLPR200F, go to
www.ti.com and search keyword "DLPR200".
Electrically, the DLP5500 consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a square
grid of 1024 memory cell columns by 768 memory cell rows. The CMOS memory array is written to on a
column-by-column basis, over a 16-bit Low Voltage Differential Signaling (LVDS) double data rate (DDR) bus.
Row addressing is handled via a serial control bus. The specific CMOS memory access protocol is handled by
the DLPC200 Digital Controller.
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated