CY74FCT821T Datasheet, PDF (1/10 Pages) Texas Instruments – 8-/9-/10-Bit Bus Interface Registers

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT821T
CY74FCT823T
CY74FCT825T
SCCS033 - May 1994 - Revised March 2000
8-/9-/10-Bit Bus Interface Registers
Features
• Function, pinout, and drive compatible with FCT, F, and
Am29821/23/25 logic
• FCT-C speed at 6.0 ns max.
FCT-B speed at 7.5 ns max.
• Reduced V_OH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• ESD > 2000V
• Sink current
Source current
64 mA
32 mA
• High-speed parallel registers with positive
edge-triggered D-type flip-flops
• Buffered common clock enable (EN) and asynchronous
clear input (CLR)
• Extended commercial range of −40˚C to +85˚C
Functional Description
These bus interface registers are designed to eliminate the
extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses
carrying parity. The FCT821T is a buffered, 10-bit wide version
of the popular FCT374 function. The FCT823T is a 9-bit wide
buffered register with clock enable (EN) and clear (CLR) ideal
for parity bus interfacing in high-performance micropro-
grammed systems. The FCT825T is an 8-bit buffered register
with all the FCT823T controls plus multiple enables (OE₁,
OE₂, OE₃) to allow multiuser control of the interface, e.g., CS,
DMA, and RD/WR. They are ideal for use as an output port
requiring high I_OL/I_OH.
These devices are designed for high-capacitance load drive
capability, while providing low-capacitance bus loading at both
inputs and outputs. Outputs are designed for low-capacitance
bus loading in the high-impedance state and are designed with
a power-off disable feature to allow for live insertion of boards.
Logic Block Diagram
D₀
D₁
D₂
D₃
D₄
D₅
D_{N- 1}
D_N
EN ^[1]
[1]
CLR
CP
OE
CL
DQ
CP
Q
CL
DQ
CP
Q
CL
DQ
CP
Q
CL
DQ
CP
Q
CL
DQ
CP
Q
CL
DQ
CP
Q
CL
DQ
CP
Q
CL
DQ
CP
Q
Y₀
Y₁
Y₂
Y₃
Y₄
Y₅
Y_{n- 1}
Y_n
Note:
1. Not on FCT821.
Copyright © 2000, Texas Instruments Incorporated