CY74FCT652T Datasheet, PDF (1/7 Pages) Texas Instruments – 8-Bit Registered Transceiver

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT652T
SCCS032 - September 1994 - Revised March 2000
8-Bit Registered Transceiver
Features
• Function, pinout, and drive compatible with FCT and
F logic
• FCT-C speed at 5.4 ns max. (Com’l)
FCT-A speed at 6.3 ns max. (Com’l)
• Reduced V_OH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• Sink Current
Source Current
64 mA
32 mA
• Independent register for A and B buses
• Multiplexed real-time and stored data transfer
• Extended commercial range of −40˚C to +85˚C
Functional Description
The FCT652T consists of bus transceiver circuits, D-type
flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the
internal storage registers. GAB and GBA control pins are
provided to control the transceiver functions. SAB and SBA
control pins are provided to select either real-time or stored
data transfer. The circuitry used for select control will eliminate
the typical decoding glitch that occurs in a multiplexer during
the transition between stored and real-time data. A LOW input
level selects real-time data and a HIGH selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by LOW-to-HIGH transitions at the
appropriate clock pins (CPAB or CPBA), regardless of the
select or enable control pins. When SAB and SBA are in the
real-time transfer mode, it is also possible to store data without
using the internal D-type flip-flops by simultaneously enabling
GAB and GBA. In this configuration, each output reinforces its
input. Thus, when all other data sources to the two sets of bus
lines are at high impedance, each set of bus lines will remain
at its last state.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
Pin Configurations
CPBA
GAB
SBA
SAB
GBA
CPAB
A₁
1 OF 8 CHANNELS
A REG
D
C
B REG
D
C
TO 7 OTHER CHANNELS
LCC
Top View
A₇
A₈
GND
NC
B₈
B₇
B₆
11 10 9 8 7 6 5
12
4
13
3
14
2
15
1
16
28
17
27
18
26
19 20 21 22 2324 25
GAB
SAB
CPAB
NC
V_CC
CPBA
SBA
B_{1 CPAB}
SAB
GAB
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
GND
SOIC/QSOP
Top View
1
24 VCC
2
23 CPBA
3
22 SBA
4
21 GBA
5
20 B1
6
19 B2
7
18 B3
8
17 B4
9
16 B5
10
15 B6
11
14 B7
12
13 B8
Copyright © 2000, Texas Instruments Incorporated