CY74FCT2652T Datasheet, PDF (1/7 Pages) Texas Instruments – 8-Bit Registered Transceiver

1CY54/
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT2652T
SCCS044 - May 1994 - Revised March 2000
8-Bit Registered Transceiver
Features
• Function and pinout compatible with FCT and F logic
• FCT-C speed at 5.4 ns max. (Com’l)
FCT-A speed at 6.3 ns max. (Com’l)
• 25Ω output series resistors to reduce transmission line
reflection noise
• Reduced V_OH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• Sink current
12 mA
Source current 15 mA
• ESD > 2000V
• Independent register for A and B buses
• Multiplexed real-time and stored data transfer
• Extended commercial temp. range of –40˚C to +85˚C
Functional Description
The FCT2652T consists of bus transceiver circuits, D-type
flip-flops, and control circuitry arranged for multiplexed trans-
mission of data directly from the input bus or from the internal
storage registers. GAB and GBA control pins are provided to
control the transceiver functions. SAB and SBA control pins are
provided to select either real-time or stored data transfer.
The circuitry used for select control will eliminate the typical
decoding glitch that occurs in a multiplexer during transition
between stored and real-time data. A LOW input level selects
real-time data and a HIGH selects stored data. Data on the A
or B data bus, or both, can be stored in the internal D flip-flops
by LOW-to-HIGH transitions at the appropriate clock pins
(CPAB or CPBA), regardless of the select or enable control
pins. When SAB and SBA are in the real-time transfer mode,
it is also possible to store data without using the internal
D-type flip-flops by simultaneously enabling GAB and GBA. In
this configuration, each output reinforces its input. Thus, when all
other data sources to the two sets of bus lines are at high imped-
ance, each set of bus lines will remain at its last state.
On-chip termination resistors are added to the outputs to
reduce system noise caused by reflections. The FCT2652T
can replace the FCT652T to reduce noise in existing designs.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards
LogicBlockDiagram
CPBA
GAB
Pin Configurations
SBA
SAB
GBA
CPAB
A1
1 OF8 CHANNELS
A REG
D
C
B REG
D
C
SOIC/QSOP
Top View
CPAB 1
SAB 2
24 V_CC
23 CPBA
GAB 3
22 SBA
A₁ 4
21 GBA
A₂ 5
20 B1
A₃ 6
19 B2
A_{4 7}
18 ^B3
B1
A₅ 8
A_{6 9}
17 ^B4
16 B5
A₇ 10
15 ^B6
A_{8 11}
14 ^B7
GND ₁₂
13 ^B8
FCT2652T–3
TO 7 OTHERCHANNELS
FCT2652T–1
Copyright © 2000, Texas Instruments Incorporated