CY74FCT2646T Datasheet, PDF (1/7 Pages) Texas Instruments – 8-Bit Registered Transceiver

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT2646T
SCCS043 - September 1994 - Revised March 2000
8-Bit Registered Transceiver
Features
• Function and pinout compatible with FCT and F logic
• FCT-C speed at 5.4 ns max.
FCT-A speed at 6.3 ns max.
• Reduced V_OH (typically = 3.3V) versions of equivalent
FCT functions
• 25Ω output series resistors to reduce transmission line
reflection noise
• Reduced V_OH (typically=3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature permits live insertion
• Matched rise and fall times
• ESD > 2000V
• Fully compatible with TTL input and output logic levels
• Sink current
12 mA
Source current 15 mA
• Independent register for A and B buses
• Extended commercial temp. range of –40˚C to +85˚C
• Three-state output
Functional Description
The FCT2646T consists of a bus transceiver circuit with
three-state, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus or
from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes to
a HIGH logic level. Enable Control G and direction pins are
provided to control the transceiver function. On-chip termina-
tion resistors have been added to the outputs to reduce system
noise caused by reflections so that the FCT2646T can be used
to replace the FCT646T in an existing design.
In the transceiver mode, data present at the high impedance
port may be stored in either the A or B register, or in both.
Select controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus will
receive data when the enable control G is Active LOW. In the
isolation mode (enable control G HIGH), A data may be stored
in the B register and/or B data may be stored in the A register.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Functional Block Diagram
G
DIR
CPBA
SBA
CPAB
SAB
D
C
A₁
D
C
Pin Configurations
QSOP
Top View
CPAB 1
SAB 2
DIR 3
A₁ 4
A_{2 5}
A_{3 6}
A_{4 7}
A_{5 8}
A_{6 9}
A₇ 10
A₈ 11
GND 12
24 V_CC
23 CPBA
22 SBA
21 G
20 B1
19 B2
18 ^B3
17 ^B4
16 ^B5
15 ^B6
14 ^B7
13 ^B8
B₁
FCT2646T –3
Logic Block Diagram
TO 7 OTHER CHANNELS
FCT2646T–1
A₁ A₂ A₃ A₄ A₅ A₆ A₇ A₈
CPAB
SAB
DIR
CPBA
SBA
G
B₁ B₂ B₃ B₄ B₅ B₆ B₇ B₈
FCT2646T–4
Copyright © 2000, Texas Instruments Incorporated