CY74FCT2543T Datasheet, PDF (1/6 Pages) Texas Instruments – 8-Bit Latched Transceiver

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT2543T
SCCS042 - September 1994 - Revised March 2000
8-Bit Latched Transceiver
Features
• Function and pinout compatible with FCT and F logic
• FCT-C speed at 5.3 ns max.
FCT-A speed at 6.5 ns max.
• 25Ω output series resistors to reduce transmission line
reflection noise
• Reduced V_OH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• Sink current
12 mA
Source current 15 mA
• Separation controls for data flow in each direction
• Back to back latches for storage
• ESD > 2000V
• Extended commercial temp. range of –40˚C to +85˚C
Functional Description
The FCT2543T Octal Latched Tranceiver contains two sets of
eight D-type latches. Separate Latch Enable (LEAB, LEBA)
and Output Enable (OEAB, OEBA) permits each latch set to
have independent control of inputting and outputting in either
direction of data flow. For data flow from A to B, for example,
the A-to-B Enable (CEAB) input must be LOW to enter data
from A or to take data from B, as indicated in the truth table.
With CEAB LOW, a LOW signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a subse-
quent LOW-to-HIGH transition of the LEAB signal puts the A
latches in the storage mode and their output no longer change
with the A inputs. With CEAB and OEAB both LOW, the
three-state B output buffers are active and reflect data present
at the output of the A latches. Control of data from B to A is
similar, but uses CEAB, LEAB, and OEAB inputs. On-chip ter-
mination resistors have been added to the outputs to reduce
system noise caused by reflections. The FCT2543T can be
used to replace the FCT543T to reduce noise in an existing
design.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Functional Block Diagram
Pin Configurations
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
OEBA
CEBA
LEBA
DQ
LE
Detail A
QD
LE
Detail A x 7
B₀
B₁
B₂
B₃
B₄
B₅
B₆
B₇
OEAB
CEAB
LEAB
FCT2543T–1
SOIC/QSOP
Top View
LEBA 1
OEBA 2
A₀ 3
A₁ 4
A₂ 5
A₃ 6
A₄ 7
A₅ 8
A₆ 9
A₇ 10
CEAB 11
GND 12
24 VCC
23 CEBA
22 B0
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 LEAB
13 OEAB
FCT2543T–3
Copyright © 2000, Texas Instruments Incorporated