CY74FCT163952 Datasheet, PDF (1/6 Pages) Texas Instruments – 16-Bit Registered Transceivers

1CY74FCT163952
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT163952
CY74FCT163H952
SCCS048 - March 1997 - Revised March 2000
16-Bit Registered Transceivers
Features
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.4 ns
• Latch-up performance exceeds JEDEC standard no. 17
• Typical output skew < 250 ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical V_olp (ground bounce) performance exceeds Mil
Std 883D
• V_CC = 2.7V to 3.6V
• ESD (HBM) > 2000V
CY74FCT163H952
• Bus hold on data inputs
• Eliminates the need for external pull-up or pull-down
resistors
• Devices with bus hold are not recommended for trans-
lating rail-to-rail CMOS signals to 3.3V logic levels
Functional Description
These 16-bit registered transceivers are high-speed,
low-power devices. 16-bit operation is achieved by connecting
the control lines of the two 8-bit registered transceivers
together. For data flow from bus A-to-B, CEAB must be LOW
to allow data to be stored when CLKAB transitions from
LOW-to-HIGH. The stored data will be present on the output
when OEAB is LOW. Control of data from B-to-A is similar and
is controlled by using the CEBA, CLKBA, and OEBA inputs.
The outputs are 24-mA balanced output drivers with current
limiting resistors to reduce the need for external terminating
resistors and provide for minimal undershoot and reduced
ground bounce.
The CY74FCT163H952 has “bus hold” on the data inputs,
which retains the input’s last state whenever the source driving
the input goes to high impedance. This eliminates the need for
pull-up/down resistors and prevents floating inputs.
The CY74FCT163952 is designed with inputs and outputs
capable of being driven by 5.0V buses, allowing its use in
mixed voltage systems as a translator. The outputs are also
designed with a power off disable feature enabling its use in
applications requiring live insertion.
Logic Block Diagrams; CY74FCT163952, CY74FCT163H952
1 ^CEBA
1 ^CLKBA
1 ^OEAB
1 ^CEAB
1 ^CLKAB
1 ^OEBA
1^A1
C
CE
D
C
CE
D
2 ^CEBA
2 ^CLKBA
2 ^OEAB
2 ^CEAB
2 ^CLKAB
2 ^OEBA
1^B1
2^A1
C
CE
D
2^B1
C
CE
D
TO7 OTHERCHANNELS
TO7 OTHERCHANNELS
Pin Configuration
SSOP/TSSOP
Top View
1^OEAB 1
1 ^CLKAB 2
1^CEAB 3
GND ⁴
1^A1 5
1^A2 6
V_CC 7
1^A3 8
1^A4 ⁹
1^A5 10
GND 11
1^A6 12
1^A7 ¹³
1^A8 ¹⁴
2^A1 15
2^A2 16
2^A3 ¹⁷
GND 18
2^A4 19
2^A5 20
2^A6 21
V_CC 22
2^A7 23
2^A8 24
GND 25
2^{CEAB 26}
2 ^{CLKAB 27}
2^{OEAB 28}
56 ₁OEBA
55 1 CLKBA
54 1CEBA
53 _GND
52 1B1
51 1B2
50 VCC
49 1B3
48 _1B4
47 1B5
46 GND
45 1B6
44 ₁B₇
43 ₁B₈
42 2^B1
41 2B2
40 ₂B₃
39 GND
38 2B4
37 2B5
36 2B6
35 VCC
34 2B7
33 2B8
32 GND
31 ₂CEBA
30 ₂ CLKBA
29 ₂OEBA
Copyright © 2000, Texas Instruments Incorporated