CY74FCT163543 Datasheet, PDF (1/7 Pages) Texas Instruments – 16-Bit Latched Transceiver

1CY74FCT163543
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT163543
SCCS063A - June 1997 - Revised April 2000
16-Bit Latched Transceiver
Features
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 5.1 ns
• Latch-up performance exceeds JEDEC standard no. 17
• ESD > 2000V per MIL-STD-883D, Method 3015
• Typical output skew < 250 ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical V_olp (ground bounce) performance exceeds Mil
Std 883D
• V_CC = 2.7V to 3.6V
Functional Description
The CY74FCT163543 is a 16-bit, high-speed, low power latched
transceiver that is organized as two independent 8-bit D-type latched
transceivers, containing two sets of eight D-type latches with separate
Latch Enable (LEAB, LEAB) and Output Enable (OEAB, OEAB) con-
trols for each set to permit independent control of inputting and out-
putting in either direction of data flow. For data flow from A to B, for
example, the A-to-B input Enable (CEAB) must be LOW in order to
enter data from A or to take data from B, as indicated in the truth table.
With CAEB LOW, a LOW signal on the A-to-B Latch Enable (LEAB)
makes the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the LEAB signal puts the A latches in the storage mode
and their outputs no longer follow the A inputs. With CEAB and OEAB
both LOW, the three-state B output buffers are active and reflect the
data present at the output of the A latches. Control of data from B to
A is similar, but uses CEAB, LEAB, and OEAB inputs.
The CY74FCT163543 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The inputs
and outputs are capable of being driven by 5.0V buses, allow-
ing them to be used in mixed voltage systems as translators.
The outputs are also designed with a power off disable feature
enabling them to be used in applications requiring live inser-
tion. Flow-through pinout and small shrink packaging simplify board
design.
Logic Block Diagrams
1OEBA
1CEBA
1^LEBA
1OEAB
1^CEAB
1LEAB
1A 1
C
D
1B1
C
D
2OEBA
2CEBA
2LEBA
2^OEAB
2CEAB
2^LEAB
2A 1
TO 7 OTHER CHANNELS
C
D
2B1
C
D
TO 7 OTHER CHANNELS
Pin Configuration
Top View
SSOP/TSSOP
1^OEAB 1
1^{LEAB 2}
1^CEAB 3
GND 4
1^A 1 5
1^A 2 ⁶
VCC 7
1A 3 8
1A 4 9
1A 5 10
GND 11
1A 6 12
1^A 7 ¹³
1A 8 14
2A 1 ¹⁵
2A 2 ¹⁶
2^A 3 ¹⁷
GND 18
2A 4 19
2^A 5 20
2^A 6 ²¹
V_CC 22
2A 7 23
2A 8 24
GND ²⁵
2^{CEAB 26}
2LEAB ²⁷
2OEAB 28
56 1OEBA
55 ₁LEBA
54 1CEBA
53 GND
52 1B1
51 ₁B₂
50 VCC
49 1B3
48 ₁B₄
47 ₁B₅
46 GND
45 1B6
44 ₁B₇
43 ₁B₈
42 _2B1
41 _2B2
40 ₂B₃
39 GND
38 2B4
37 2B5
36 ₂B₆
35 VCC
34 2B7
33 2B8
32 _GND
31 _2CEBA
30 ₂LEBA
29 2OEBA
Copyright © 2000, Texas Instruments Incorporated