CY74FCT163501 Datasheet, PDF (1/9 Pages) Texas Instruments – 18-Bit Registered Transceivers

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT163501
CY74FCT163H501
SCCS047 - January 1998 - Revised March 2000
18-Bit Registered Transceivers
Features
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.6 ns
• Latch-up performance exceeds JEDEC standard no. 17
• ESD > 2000V per MIL-STD-883D, Method 3015
• Typical output skew < 250ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical V_olp (ground bounce) performance exceeds Mil
Std 883D
• V_CC = 2.7V to 3.6V
CY74FCT163501 Features:
• Balanced output drivers: 24 mA
• Reduced system switching noise
• Typical V_OLP (ground bounce) <0.6V at V_CC = 3.3V,
T_A= 25˚C
CY74FCT163H501 Features:
• Bus hold retains the last active state
• Devices with bus hold are not recommended for trans-
lating rail-to-rail CMOS signals to 3.3V logic levels
• Eliminates the need for external pull-up or pull-down
resistors
Functional Description
These 18-bit universal bus transceivers can be operated in
transparent, latched or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For
A-to-B data flow, the device operates in transparent mode
when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CLKAB is held at a HIGH or LOW logic level. If LEAB
is LOW, the A bus data is stored in the latch/flip-flop on the
LOW-to-HIGH transition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and
CLKBA. The output buffers are designed with a power-off
disable feature to allow live insertion of boards.
THE CY74FCT163501 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors, as well as provides for
minimal undershoot and reduced ground bounce. The
CY74FCT163501 is ideal for driving transmission lines.
The CY74FCT163H501 is a 24-mA balanced output part, that
has “bus hold” on the data inputs. The device retains the
input’s last state whenever the input goes to high impedance.
This eliminates the need for pull-up/down resistors and
prevents floating inputs.
Functional Block Diagram; CY74FCT163501, CY74FCT163H501
Pin Configuration
SSOP/TSSOP
Top View
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
A₁
C
C
D
D
C
C
D
D
TO 17 OTHER CHANNELS
FCT163501-1
OEAB 1
LEAB 2
A₁ 3
GND 4
A₂ 5
A₃ 6
V_CC 7
A₄ 8
A₅ 9
A _{6 10}
GND 11
A ₇ 12
A ₈ 13
A ₉ 14
A ₁₀ 15
B₁
A ₁₁ 16
A ₁₂ 17
GND 18
A ₁₃ 19
A ₁₄ 20
A ₁₅ 21
V_CC 22
A ₁₆ 23
A ₁₇ 24
GND 25
A ₁₈ 26
OEBA 27
LEBA 28
56 GND
55 CLKAB
54 B1
53 GND
52 B2
51 B₃
50 V_CC
49 B4
48 B₅
47 B6
46 GND
45 B₇
44 B₈
43 B₉
42 B10
41 B11
40 B₁₂
39 GND
38 B13
37 B14
36 B₁₅
35 V_CC
34 B₁₆
33 B₁₇
32 GND
31 B18
30 CLKBA
29 GND
FCT163501-2
Copyright © 2000, Texas Instruments Incorporated