CY74FCT163500 Datasheet, PDF (1/7 Pages) Texas Instruments – 18-Bit Registered Transceiver

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT163500
SCCS066 - June 1997 - Revised March 2000
18-Bit Registered Transceiver
Features
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.6 ns
• Latch-up performance exceeds JEDEC standard no. 17
• ESD > 2000V per MIL-STD-883D, Method 3015
• Typical output skew < 250ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical V_olp (ground bounce) performance exceeds Mil
Std 883D
• V_CC = 2.7V to 3.6V
Functional Description
The CY74FCT163500 is an 18-bit universal bus transceiver
that can be operated in transparent, latched, or clock modes
by combining D-type latches and D-type flip-flops. Data flow in
each direction is controlled by output-enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock inputs
(CLKAB and CLKBA) inputs. For A-to-B data flow, the device
operates in transparent mode when LEAB is HIGH. When
LEAB is LOW, the A data is latched if CLKAB is held at a HIGH
or LOW logic level. If LEAB is LOW, the A bus data is stored in
the latch/flip-flop on the HIGH-to-LOW transition of CLKAB.
OEAB performs the output enable function on the B port. Data
flow from B-to-A is similar to that of A-to-B and is controlled by
OEBA, LEBA, and CLKBA.
The CY74FCT163500 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce.The inputs
and outputs are capable of being driven by 5.0V busses,
allowing them to be used in mixed voltage systems as
translators. The outputs are also designed with a power off
disable feature enabling them to be used in applications
requiring live insertion.
Logic Block Diagram
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
A₁
C
C
D
D
C
C
D
D
TO 17 OTHER CHANNELS
Pin Configuration
SSOP/TSSOP
Top View
OEAB 1
LEAB 2
A₁ 3
GND 4
A₂ 5
A₃ 6
V_{CC 7}
A_{4 8}
A_{5 9}
A_{6 10}
GND ₁₁
A₇ 12
A₈ ¹³
B₁
A₉ 14
A₁₀ 15
A₁₁ 16
A₁₂ 17
GND 18
A_{13 19}
A₁₄ 20
A₁₅ 21
V_CC 22
A₁₆ 23
A_{17 24}
GND 25
A₁₈ 26
OEBA ₂₇
LEBA ₂₈
56 GND
55 ^CLKAB
54 B1
53 GND
52 B2
51 ^B3
50 VCC
49 ^B4
48 ^B5
47 ^B6
46 GND
45 B7
44 B₈
43 B₉
42 B10
41 B₁₁
40 B₁₂
39 GND
38 ^B13
37 B14
36 B₁₅
35 V_CC
34 B₁₆
33 B₁₇
32 GND
31 B18
30 ^CLKBA
29 ^GND
Copyright © 2000, Texas Instruments Incorporated