CY74FCT16240T Datasheet, PDF (1/11 Pages) Texas Instruments – 16-Bit Buffers/Line Drivers

1CY74FCT162240T
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16240T
CY74FCT162240T
SCCS027B - August 1994 - Revised September 2001
Features
• I_off supports partial-power-down mode operation
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of –40˚C to +85˚C
• V_CC = 5V ± 10%
CY74FCT16240T Features:
• 64 mA sink current, 32 mA source current
• Typical V_OLP (ground bounce)
<1.0V at V_CC = 5V, T_A = 25˚C
CY74FCT162240T Features:
• Balanced output drivers: 24 mA
• Reduced system switching noise
• Typical V_OLP (ground bounce)
<0.6V at V_CC = 5V, T_A= 25˚C
Logic Block Diagrams
1^OE
1^A1
1^A2
1^A3
1^A4
2^OE
2^A1
2^A2
2^A3
2^A4
1^Y1
1^Y2
1^Y3
1^Y4
FCT16240–1
2^Y1
2^Y2
2^Y3
2^Y4
FCT16240–2
3^OE
3^A1
3^A2
3^A3
3^A4
4^OE
4^A1
4^A2
4^A3
4^A4
16-Bit Buffers/Line Drivers
Functional Description
These 16-bit buffer/line drivers are used in memory driver,
clock driver, or other bus interface applications, where high
speed and low power are required. With flow-through pinout
and small shrink packaging, board layout is simplified. The
three-state controls are designed to allow 4-, 8-, or 16-bit
operation.
This device is fully specified for partial-power-down
applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device
when it is powered down.
The CY74FCT16240T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162240T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for mini-
mal undershoot and reduced ground bounce. The
CY74FCT162240T is ideal for driving transmission lines.
3^Y1
3^Y2
3^Y3
3^Y4
FCT16240–3
4^Y1
4^Y2
4^Y3
4^Y4
FCT16240–4
Pin Configuration
SSOP/TSSOP
Top View
1^{OE 1}
1^Y1 2
1^Y2 3
GND 4
1^Y3 5
1^Y4 6
V_{CC 7}
2^Y1 ₈
2^Y2 ₉
GND ₁₀
2^Y3 11
2^Y4 12
3^Y1 ¹³
3^Y2 ¹⁴
GND ¹⁵
3^Y3 ¹⁶
3^Y4 ¹⁷
V_CC 18
4^Y1 19
4^Y2 20
GND 21
4^Y3 22
4^Y4 23
4^OE 24
48 ₂OE
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
42 ^VCC
41 2^A1
40 ^2A2
39 ^GND
38 2^A3
37 2^A4
36 ₃A₁
35 ₃A₂
34 _GND
33 ₃A₃
32 _3A4
31 V_CC
30 4A1
29 4A2
28 GND
27 4A3
26 4A4
25 3^OE
FCT16240–5
Copyright © 2001, Texas Instruments Incorporated