CY5474FCT841T Datasheet, PDF (1/8 Pages) Texas Instruments – 10-Bit Latch

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT841T
SCCS035 - September 1994 - Revised March 2000
10-Bit Latch
Features
• Function, pinout, and drive compatible with FCT, F, and
AM29841 logic
• FCT-C speed at 5.5 ns max. (Com’l)
FCT-B speed at 6.5 ns max. (Com’l)
• Reduced V_OH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• ESD > 2000V
• Fully compatible with TTL input and output logic levels
• Sink current
Source current
64 mA (Com’l),
32 mA (Mil)
32 mA (Com’l),
12 mA (Mil)
• High-speed parallel latches
• Buffered common latch enable input
Functional Description
The FCT841T bus interface latch is designed to eliminate the
extra packages required to buffer existing latches and provide
extra data width for wider address/data paths or buses
carrying parity. The FCT841T is a buffered 10-bit wide version
of the FCT373 function.
The FCT841T high-performance interface is designed for
high-capacitance load drive capability while providing
low-capacitance bus loading at both inputs and outputs.
Outputs are designed for low-capacitance bus loading in the
high impedance state and are designed with a power-off
disable feature to allow for live insertion of boards.
Functional Block Diagram
D₀
D₁
D₂
D₃
D₄
D₅
D_{N- 1}
D_N
D
LE Q
DQ
LE Q
DQ
LE Q
DQ
LE Q
DQ
LE Q
DQ
LE Q
DQ
LE Q
DQ
LE Q
LE
OE
Y₀
Y₁
Y₂
Logic Block Diagram
D
10
LE
OE
D
Q
LE
10
Y
Y₃
Y₄
Y₅
Y_{N- 1}
Y_N
Pin Configurations
DIP/QSOP/SOIC
Top View
OE 1
D₀ 2
D₁ 3
D₂ 4
D₃ 5
D₄ 6
D₅ 7
D₆ 8
D₇ 9
D₈ 10
D₉ 11
GND 12
24 V_CC
23 Y₀
22 Y₁
21 Y₂
20 Y3
19 Y4
18 Y5
17 Y6
16 Y₇
15 ^Y8
14 Y9
13 LE
Copyright © 2000, Texas Instruments Incorporated