CY5474FCT646T Datasheet, PDF (1/8 Pages) Texas Instruments – 8-Bit Registered Transceiver

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT646T
SCCS031 - July 1994 - Revised March 2000
8-Bit Registered Transceiver
Features
• Function, pinout, and drive compatible with FCT and
F logic
• FCT-C speed at 5.4 ns max. (Com’l)
FCT-A speed at 6.3 ns max. (Com’l)
• Reduced V_OH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature permits live insertion
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• ESD > 2000V
• Sink current
Source current
64 mA (Com’l), 48 mA (Mil)
32 mA (Com’l), 12 mA (Mil)
• Independent register for A and B buses
• Extended commercial range of −40˚C to +85˚C
Function Block Diagrams
G
DIR
CPBA
SBA
CPAB
SAB
D
C
A₁
D
C
TO 7 OTHER CHANNELS
Functional Description
The FCT646T consists of a bus transceiver circuit with
three-state, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus or
from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes to
a HIGH logic level. Enable Control G and direction pins are
provided to control the transceiver function. In the transceiver
mode, data present at the high-impedance port may be stored
in either the A or B register, or in both. The select controls can
multiplex stored and real-time (transparent mode) data. The
direction control determines which bus will receive data when
the enable control G is Active LOW. In the isolation mode
(enable Control G HIGH), A data may be stored in the B reg-
ister and/or B data may be stored in the A register.
The outputs of the FCT646T are designed with a power-off
disable feature to allow for live insertion of boards.
Pin Configurations
LCC
Top View
QSOP, SOIC
Top View
CPAB 1
SAB 2
A₇
A₈
GND
NC
B₈
B₇
B₆
11 10 9 8 7 6 5
12
4
13
3
14
2
15
1
16
28
17
27
18
26
19 20 21 22 23 24 25
DIR
SAB
CPAB
NC
V_CC
CPBA
SBA
DIR 3
A₁ 4
A₂ 5
A₃ 6
A_{4 7}
A_{5 8}
A₆ 9
A₇ 10
A₈ 11
GND ₁₂
24 VCC
23 CPBA
22 SBA
21 G
20 B1
19 B2
18 ^B3
17 ^B4
16 ^B5
15 ^B6
14 ^B7
13 ^B8
B_{1 Logic Block Diagram}
A₁ A₂ A₃ A₄ A₅ A₆ A₇ A₈
CPAB
SAB
DIR
CPBA
SBA
G
B₁ B₂ B₃ B₄ B₅ B₆ B₇ B₈
Pin Description
Name
A
B
CPAB, CPBA
SAB, SBA
DIR, G
Description
Data Register A Inputs, Data Register B Outputs
Data Register B Inputs, Data Register A Outputs
Clock Pulse Inputs
Output Data Source Select Inputs
Output Enable Inputs
Copyright © 2000, Texas Instruments Incorporated