CY5474FCT540T Datasheet, PDF (1/8 Pages) Texas Instruments – 8-Bit Buffers/Line Drivers

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT540T
CY54/74FCT541T
SCCS029 - May 1994 - Revised March 2000
8-Bit Buffers/Line Drivers
Features
• Function, pinout, and drive compatible with FCT and
F logic
• FCT-C speed at 4.1 ns max. (Com’l)
FCT-A speed at 4.8 ns max. (Com’l)
• Reduced V_OH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• ESD > 2000V
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• Sink current
Source current
64 mA (Com’l), 48 mA (Mil)
32 mA (Com’l), 12 mA (Mil)
• Extended commercial range of −40˚C to +85˚C
Functional Description
The FCT540T inverting buffer/line driver and the FCT541T
non-inverting buffer/line driver are designed to be employed as
memory address drivers, clock drivers, and bus-oriented
transmitters/receivers. The devices provide speed and drive
capabilities equivalent to their fastest bipolar logic
counterparts while reducing power dissipation. The input and
output voltage levels allow direct interface with TTL, NMOS,
and CMOS devices without external components.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram—FCT540T
OE_A
OE_B
D₀
O₀
D₁
O₁
D₂
O₂
D₃
O₃
D₄
O₄
D₅
O₅
D₆
O₆
D₇
O₇
Pin Configurations
CERDIP/SOIC/QSOP
Top View
OE_A
D₀
D₁
D₂
D₃
D₄
D₅
D₆
D₇
GND
1
20
2
19
3
18
4
17
5
16
FCT540T
6
15
7
14
8
13
9
12
10
11
V_CC
OE_B
O₀
O₁
O₂
O₃
O₄
O₅
O₆
O₇
Logic Block Diagram—FCT541T
OE_A
OE_B
D₀
O₀
D₁
O₁
D₂
O₂
D₃
O₃
D₄
O₄
D₅
O₅
D₆
O₆
D₇
O₇
CERDIP/DIP/SOIC/QSOP
Top View
OE_A
D₀
D₁
D₂
D₃
D₄
D₅
D₆
D₇
GND
1
20
2
19
3
18
4
17
5 _FCT541T 16
6
15
7
14
8
13
9
12
10
11
V_CC
OE_B
O₀
O₁
O₂
O₃
O₄
O₅
O₆
O₇
Copyright © 2000, Texas Instruments Incorporated