CY5474FCT377T Datasheet, PDF (1/7 Pages) Texas Instruments – 8-Bit Register

1CY54/74FCT377T
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT377T
SCCS023 - May1994 - Revised March 2000
Features
• Function, pinout and drive compatible with FCT and
F logic
• FCT-C speed at 5.2 ns max. (Com’l)
FCT-A speed at 7.2 ns max. (Com’l)
• Reduced V_OH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• ESD > 2000V
• Fully compatible with TTL input and output logic levels
• Sink Current
Source Current
64 mA (Com’l),
32 mA (Mil)
32 mA (Com’l),
12 mA (Mil)
Logic Block Diagram
8-Bit Register
• Clock Enable for address and data synchronization
application
• Eight edge-triggered D flip-flops
• Extended commercial range of −40˚C to +85˚C
Functional Description
The FCT377T has eight triggered D-type flip-flops with
individual D inputs. The common buffered clock inputs (CP)
loads all flip-flops simultaneously when the Clock Enable (CE)
is LOW. The register is fully edge-triggered. The state of each
D input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s O out-
put. The CE input must be stable only one set-up time prior to
the LOW-to-HIGH clock transition for predictable operation.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
D₀
D₁
D₂
D₃
D₄
D₅
D₆
D₇
CE
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
CP
O₀
O₁
O₂
O₃
O₄
O₅
O₆
O₇
Pin Configurations
LCC
Top View
8 7 654
O_{3 9}
3 ^D0
GND ₁₀
CP ₁₁
2 ^O0
1 ^CE
O_{4 12}
20 ^VCC
D₄ 13
19 ^O7
14 1516 17 18
CE
O₀
D₀
D₁
O₁
O₂
D₂
D₃
O₃
GND
SOIC/QSOP
Top View
1
20 VCC
2
19 O7
3
18 ^D7
4
17 ^D6
5
16 ^O6
6
15 ^O5
7
14 D5
8
13 D4
9
12 O4
10
11 CP
Logic Symbol
D₀ D₁ D₂ D₃ D₄ D₅ D₆ D₇
CP
CE
O₀ O₁ O₂ O₃ O₄ O₅ O₆ O₇
Copyright © 2000, Texas Instruments Incorporated