CY5474FCT273T Datasheet, PDF (1/7 Pages) Texas Instruments – 8-Bit Register

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT273T
SCCS020 - March 1995 - Revised February 2000
Features
• Function, pinout, and drive compatible with FCT and
F logic
• FCT-C speed at 5.8 ns max. (Com’l)
FCT-A speed at 7.2 ns max. (Com’l)
• Reduced V_OH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• ESD > 2000V
• Fully compatible with TTL input and output logic levels
• Extended commercial range of −40˚C to +85˚C
• Sink current
Source current
64 mA (Com’l), 32 mA (Mil)
32 mA (Com’l), 12 mA (Mil)
8-Bit Register
Functional Description
The FCT273T consists of eight edge-triggered D-type
flip-flops with individual D inputs and Q outputs. The common
buffered clock (CP) and master reset (MR) load and reset all
flip-flops simultaneously. The FCT273T is an edge-triggered
register. The state of each D input (one set-up time before the
LOW-to-HIGH clock transition) is transferred to the corre-
sponding flip-flop’s Q output. All outputs will be forced LOW by
a low voltage level on the MR input.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
D₀
D₁
D₂
D₃
D₄
D₅
D₆
D₇
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
R_D
R_D
R_D
R_D
MR
Q₀
Q₁
Q₂
Q₃
Pin Configurations
LCC
Top View
8 7 654
Q_{3 9}
3 ^D0
GND 10
2 ^Q0
CP 11
1 ^MR
Q_{4 12}
20 ^VCC
D₄ 13
19 ^Q7
14 1516 17 18
FCT273T–2
DIP/SOIC/QSOP
Top View
MR ₁
Q_{0 2}
D₀ 3
D₁ 4
Q_{1 5}
Q₂ 6
D_{2 7}
D₃ 8
Q₃ 9
GND 10
20 VCC
19 Q7
18 ^D7
17 ^D6
16 ^Q6
15 ^Q5
14 D5
13 D4
12 Q4
11 CP
FCT273T–3
R_D
R_D
R_D
Q₄
Q₅
Q₆
Logic Symbol
R_D
Q₇
FCT273T–1
D₀ D₁ D₂ D₃ D₄ D₅ D₆ D₇
CP
MR
Q₀ Q₁ Q₂ Q₃ Q₄ Q₅ Q₆ Q₇
FCT273T–4
Function Table^[1]
Inputs
Output
Operating Mode MR
CP
D
Q
Reset (clear)
L
X
X
L
Load ‘1’
H
h
H
Load ‘0’
H
l
L
Note:
1. H
h
L
l
X
= HIGH Voltage Level steady state
= HIGH Voltage Level one set-up time prior to LOW-to-HIGH clock transition
= LOW Voltage Level steady state
= LOW Voltage Level one set-up time prior to the LOW-to-HIGH transition
= Don’t Care
= LOW-to-HIGH clock transition
Copyright © 2000, Texas Instruments Incorporated