CDCVF857 Datasheet, PDF (1/19 Pages) Texas Instruments – 2.5-V PHASE-LOCK LOOP CLOCK DRIVER

CDCVF857
2.5ĆV PHASEĆLOCK LOOP CLOCK DRIVER
D Recommended Applications:
− DDR Memory Modules
(DDR400/333/266/200)
− Zero Delay Fan-Out Buffer
D Spread Spectrum Clock Compatible
D Operating Frequency: 60 MHz to 220 MHz
D Low Jitter (Cycle-Cycle): ±35 ps
D Low Static Phase Offset: ±50 ps
D Low Jitter (Period): ±30 ps
D 1-To-10 Differential Clock Distribution
(SSTL2)
D Best in Class for V_OX = V_DD/2 ±0.1 V
SCAS047D − MARCH 2003 − REVISED JUNE 2005
D Operates From Dual 2.6-V or 2.5-V Supplies
D Available in a 40-Pin MLF Package, 48-Pin
TSSOP Package, 56-Ball MicroStar Junior
BGA Package
D Consumes < 100-µA Quiescent Current
D External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
D Meets/Exceeds JEDEC Standard
(JESD82−1) For DDRI-200/266/333
Specification
D Meets/Exceeds Proposed DDRI-400
Specification (JESD82−1A)
D Enters Low-Power Mode When No CLK
Input Signal Is Applied or PWRDWN Is Low
description
The CDCVF857 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock
input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback
clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback
clocks (FBIN, FBIN), and the analog power input (AV_DD). When PWRDWN is high, the outputs switch in phase
and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state)
and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input
frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input
frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this
detection circuit turns the PLL on and enables the outputs.
When AV_DD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCVF857 is also able
to track spread spectrum clocking for reduced EMI.
Because the CDCVF857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the
PLL. This stabilization time is required following power up. The CDCVF857 is characterized for both commercial
and industrial temperature ranges.
AVAILABLE OPTIONS
TA
TSSOP (DGG)
40-Pin MLF
56-Ball BGA ^†
−40°C to 85°C
CDCVF857DGG
(Pb-Free)
CDCVF857RTB
CDCVF857GQL
−40°C to 85°C
CDCVF857RHA
(Pb-Free, Green)
† _{Maximum load recommended is 12 pf for 200 MHz. At 12-pf load, maximum TA allowed is 70°C.}
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2005, Texas Instruments Incorporated
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