CDCVF2505 Datasheet, PDF (1/10 Pages) Texas Instruments – 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER

CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
D Phase-Lock Loop Clock Driver for
Synchronous DRAM and General-Purpose
Applications
D Spread Spectrum Clock Compatible
D Operating Frequency: 24 MHz to 200 MHz
D Low Jitter (Cycle-cycle): <|150 ps| Over the
Range 66 MHz–200 MHz
D Distributes One Clock Input to One Bank of
Five Outputs (CLKOUT Is Used to Tune the
Input-Output Delay)
D Three-States Outputs When There Is no
Input Clock
D Operates From Single 3.3-V Supply
D Available in 8-Pin TSSOP and 8-Pin SOIC
Packages
D Consumes Less Than 100 µA (Typically) in
Power Down Mode
D Internal Feedback Loop Is Used to
Synchronize the Outputs to the Input Clock
D 25-Ω On-Chip Series Damping Resistors
D Integrated RC PLL Loop Filter Eliminates
the Need for External Components
SCAS640D – JULY 2000 – REVISED JULY 2002
D OR PW PACKAGE
(TOP VIEW)
CLKIN 1
1Y1 2
1Y0 3
GND 4
8 CLKOUT
7 1Y3
6 V_DD 3.3 V
5 1Y2
description
The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock
signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that
make it ideal for driving point-to-point loads.
One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50
percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input
signal is applied to CLKIN.
Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop
filter for the PLLs is included on-chip, minimizing component count, space, and cost.
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This stabilization is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.
The CDCVF2505 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2002, Texas Instruments Incorporated
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