CDCV857 Datasheet, PDF (1/12 Pages) Texas Instruments – 2.5-V PHASE LOCK LOOP CLOCK DRIVER

CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
D Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM
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Applications
D Spread Spectrum Clock Compatible
D Operating Frequency: 60 to 200 MHz
D Low Jitter (cyc–cyc): ±75 ps
D Distributes One Differential Clock Input to
GND 1
Y0 2
Y0 3
V_DDQ 4
Y1 5
48 GND
47 Y5
46 Y5
45 V_DDQ
44 Y6
Ten Differential Outputs
D Three-State Outputs When the Input
Differential Clocks Are <20 MHz
D Operates From Dual 2.5-V Supplies
D 48-Pin TSSOP Package
D Consumes < 200-µA Quiescent Current
D External Feedback PIN (FBIN, FBIN) Are
Y1 6
GND 7
GND 8
Y2 9
Y2 10
V_DDQ 11
V_DDQ 12
CLK 13
43 Y6
42 GND
41 GND
40 Y7
39 Y7
38 V_DDQ
37 PWRDWN
36 FBIN
Used to Synchronize the Outputs to the
CLK 14
35 FBIN
Input Clocks
description
V_DDQ 15
AV_DD 16
AGND 17
34 V_DDQ
33 FBOUT
32 FBOUT
The CDCV857 is a high-performance, low-skew,
low-jitter zero delay buffer that distributes a
differential clock input pair (CLK, CLK) to ten
differential pairs of clock outputs (Y[0:9], Y[0:9])
and one differential pair of feedback clock output
(FBOUT, FBOUT). The clock outputs are
controlled by the clock inputs (CLK, CLK), the
GND ¹⁸
Y3 ¹⁹
Y3 ²⁰
V_DDQ ²¹
Y4 ²²
Y4 ²³
GND ²⁴
31 _GND
30 _Y8
29 _Y8
28 _VDDQ
27 _Y9
26 _Y9
25 _GND
feedback clocks (FBIN, FBIN), and the analog
power input (AV_DD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When
PWRDWN is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power
mode). The device also enters this low power mode when the input frequency falls below a suggested detection
frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low
frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and
enables the outputs.
When AV_DD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857 is also able
to track spread spectrum clocking for reduced EMI.
Since the CDCV857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up. The CDCV857 is characterized for operation from 0°C
to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 2000, Texas Instruments Incorporated
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