CDCU877 Datasheet, PDF (1/17 Pages) Texas Instruments – 1.8V PHASE LOCK LOOP CLOCK DRIVER

D 1.8-V Phase Lock Loop Clock Driver for
Double Data Rate ( DDR II ) Applications
D Spread Spectrum Clock Compatible
D Operating Frequency: 10 MHz to 400 MHz
D Low Current Consumption: <135 mA
D Low Jitter (Cycle-Cycle): ±30 ps
D Low Output Skew: 35 ps
D Low Period Jitter: ±20 ps
D Low Dynamic Phase Offset:: ±15 ps
D Low Static Phase Offset:: ±50 ps
D Distributes One Differential Clock Input to
Ten Differential Outputs
D 52-Ball µBGA (MicroStar Junior BGA,
0,65-mm pitch) and 40-Pin MLF
CDCU877/CDCU877A
1.8ĆV PHASE LOCK LOOP CLOCK DRIVER
ą
SCAS688A − JUNE 2003 − REVISED JANUARY 2004
D External Feedback Pins ( FBIN, FBIN ) are
Used to Synchronize the Outputs to the
Input Clocks
D Single-Ended Input and Single-Ended
Output Modes
D Meets or Exceeds JESD82-8 PLL Standard
for PC2-3200/4300
D Fail-Safe Inputs
description
The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input
pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN),
the LVCMOS control pins (OE, OS), and the analog power input (AV_DD). When OE is low, the clock outputs, except
FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select)
is a program pin that must be tied to GND or V_DD. When OS is high, OE functions as previously described. When
OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AV_DD is grounded, the PLL is turned
off and bypassed for test purposes.
When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit
on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state
where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being
differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock
between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time.
The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from –40°C
to 85°C.
TA
−40°C to 85°C
−40°C to 85°C
−40°C to 85°C
−40°C to 85°C
AVAILABLE OPTIONS
52-Ball BGA
CDCU877ZQL
(Pb-Free)
CDCU877AZQL
(Pb-Free)
CDCU877GQL
CDCU877AGQL
40-Pin MLF
CDCU877RTB
CDCU877ARTB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar Junior is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2004, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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