CDCU2A877 Datasheet, PDF (1/14 Pages) Texas Instruments – 1.8-V PHASE LOCK LOOP CLOCK DRIVER

www.ti.com
1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU2A877
SCAS827 – AUGUST 2006
FEATURES
• 1.8-V/1.9-V Phase Lock Loop Clock Driver for
Double Data Rate ( DDR II ) Applications
• Spread Spectrum Clock Compatible
• Operating Frequency: 125 MHz to 410 MHz
• Application Frequency: 160 MHz to 410 MHz
• Low Jitter (Cycle-Cycle): ±40 ps
• Low Output Skew: 35 ps
• Stabilization Time <6 µs
• Distributes One Differential Clock Input to 10
Differential Outputs
• High-Drive Version of CDCUA877
• 52-Ball mBGA (MicroStar Junior™ BGA,
0,65-mm pitch)
• External Feedback Pins ( FBIN, FBIN ) are
Used to Synchronize the Outputs to the Input
Clocks
• Meets or Exceeds CUA877/CUA878
Specification PLL Standard for
PC2-3200/4300/5300/6400
• Fail-Safe Inputs
DESCRIPTION
The CDCU2A877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock
input pair (CK, CK) to 10 differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock
outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks
(FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AV_DD). When OE is low, the
clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in
frequency. OS (output select) is a program pin that must be tied to GND or V_DD. When OS is high, OE functions
as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running.
When AV_DD is grounded, the PLL is turned off and bypassed for test purposes.
When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection
circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low
power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being
logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the
PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within
the specified stabilization time.
The CDCU2A877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from
0°C to 70°C.
AVAILABLE OPTIONS
T_A
0°C to 70°C
52-Ball BGA⁽¹⁾
CDCU2A877ZQL
(1) For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see the
TI website at www.ti.com.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar Junior is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated