CDCM61001_10 Datasheet, PDF (1/35 Pages) Texas Instruments – One Output, Integrated VCO, Low-Jitter Clock Generator

CDCM61001
www.ti.com
SCAS869C – FEBRUARY 2009 – REVISED FEBRUARY 2010
One Output, Integrated VCO, Low-Jitter Clock Generator
Check for Samples: CDCM61001
FEATURES
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•2 One Crystal Reference Input Including 24.8832
MHz, 25 MHz, and 26.5625 MHz
• Input Frequency Range: 21.875 MHz to
28.47 MHz
• On-Chip VCO Operates in Frequency Range of
1.75 GHz to 2.05 GHz
• 1x Output Available:
– Pin-Selectable Between LVPECL, LVDS, or
2-LVCMOS; Operates at 3.3 V
• LVCMOS Bypass Output Available
• Output Frequency Selectable by /1, /2, /3, /4, /6,
/8 from the Output Divider
• Supports Common LVPECL/LVDS Output
Frequencies:
– 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
155.52 MHz, 156.25 MHz, 159.375 MHz,
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz,
311.04 MHz, 312.5 MHz, 622.08 MHz,
625 MHz
• Supports Common LVCMOS Output
Frequencies:
– 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
155.52 MHz, 156.25 MHz, 159.375 MHz,
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz
• Output Frequency Range: 43.75 MHz to
683.264 MHz (See Table 3)
• Internal PLL Loop Bandwidth: 400 kHz
• High-Performance PLL Core:
– Phase Noise typically at –146 dBc/Hz at
5-MHz Offset for 625-MHz LVPECL Output
– Random Jitter typically at 0.509 ps, RMS
(10 kHz to 20 MHz) for 625-MHz LVPECL
Output
• Output Duty Cycle Corrected to 50% (± 5%)
• Divider Programming Using Control Pins:
– Two Pins for Prescaler/Feedback Divider
– Three Pins for Output Divider
– Two Pins for Output Select
• Chip Enable and Device Reset Control Pins
Available
• 3.3-V Core and I/O Power Supply
• Industrial Temperature Range: –40°C to +85°C
• 5-mm × 5-mm, 32-pin, QFN (RHB) Package
• ESD Protection Exceeds 2 kV (HBM)
APPLICATIONS
• Low Jitter Clock Driver for High-End Datacom
Applications Including SONET, Ethernet, Fibre
Channel, Serial ATA, and HDTV
• Cost-Effective High-Frequency Crystal
Oscillator Replacement
DESCRIPTION
The CDCM61001 is a highly versatile, low-jitter
frequency synthesizer that can generate low-jitter
clock outputs, selectable between low-voltage
positive emitter coupled logic (LVPECL), low-voltage
differential signaling (LVDS), or low-voltage
complementary metal oxide semiconductor
(LVCMOS) outputs, from a low-frequency crystal for a
variety of wireline and data communication
applications. The CDCM61001 features an onboard
PLL that can be easily configured solely through
control pins. The overall output random jitter
performance is less than 1ps, RMS (from 10 kHz to
20 MHz), making this device a perfect choice for use
in demanding applications such as SONET, Ethernet,
Fibre Channel, and SAN. The CDCM61001 is
available in a small, 32-pin, 5-mm × 5-mm QFN
package.
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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