CDCF5801A Datasheet, PDF (1/18 Pages) Texas Instruments – CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT

CDCF5801A
www.ti.com
SCAS816 – MARCH 2006
CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
FEATURES
• Low-Jitter Clock Multiplier: ×1, ×2, ×4, ×8
• Fail-Safe Power Up Initialization
• Programmable Bidirectional Delay Steps of
1.3 mUI
• Output Frequency Range of 25 MHz to
280 MHz
• Input Frequency Range of 12.5 MHz to
240 MHz
• Low Jitter Generation
• Single-Ended REFCLK Input With Adjustable
Trigger Level (Works With LVTTL, HSTL, and
LVPECL)
• Differential/Single-Ended Output
• Output Can Drive LVPECL, LVDS, and LVTTL
• Three Power Operating Modes to Minimize
Power
• Low Power Consumption (< 190 mW at
280 MHz/3.3 V)
• Packaged in a Shrink Small-Outline Package
(DBQ)
• No External Components Required for PLL
• Spread Spectrum Clock Tracking Ability to
Reduce EMI (SSC)
APPLICATIONS
• Video Graphics
• Gaming Products
• Datacom
• Telecom
• Noise Cancellation Created by FPGAs
DBQ PACKAGE
(TOP VIEW)
VDDREF
1
REFCLK
2
VDDP
3
GNDP
4
GND
5
LEADLAG
6
DLYCTRL
7
GNDPA
8
VDDPA
9
VDDPD
10
STOPB
11
PWRDNB
12
24
P0
23
P1
22
VDDO
21
GNDO
20
CLKOUT
19
NC
18
CLKOUTB
17
GNDO
16
VDDO
15
MULT0
14
MULT1
13
P2
DESCRIPTION
The CDCF5801A provides clock multiplication from a reference clock (REFCLK) signal with the unique capability
to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising
edge on the DLYCTRL pin the CLKOUT is delayed by a 1.3-mUI step size as long as the LEADLAG input
detects a low signal at the time of the DLYCTRL rising edge. Similarly for every rising edge on the DLYCTRL pin
the CLKOUT is advanced by a 1.3-mUI step size as long as the LEADLAG pin is high during the transition. This
unique capability allows the device to phase align (zero delay) between CLKOUT/CLKOUTB and any one other
CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG pins. Also it
provides the capability to program a fixed delay by providing the proper number of edges on the DLYCTRL pin,
while strapping the LEADLAG pin to dc high or low. Further possible applications are:
• Aligning the rising edge of the output clock signal to the input clock rising edge
• Avoiding PLL instability in applications that require very long PLL feedback lines
• Isolation of jitter and digital switching noise
• Limitation of jitter in systems with good ppm frequency stability
The CDCF5801A has a fail-safe power up initialization state-machine which supports proper operation under all
power up conditions.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated