CDCF2510 Datasheet, PDF (1/11 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDCF2510
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
D Designed to Meet PC133 SDRAM
Registered DIMM Specification Rev. 0.9
D Spread Spectrum Clock Compatible
D Operating Frequency 25 MHz to 140 MHz
D Static tPhase Error Distribution at 66MHz to
133 MHz is ±125 ps
D Jitter (cyc – cyc) at 66 MHz to 133 MHz Is
|70| ps
D Available in Plastic 24-Pin TSSOP
D Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D Distributes One Clock Input to One Bank of
Ten Outputs
D Output Enable Pin to Enable/Disable All 10
Outputs
D External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input
D On-Chip Series Damping Resistors
D No External RC Network Required
D Operates at 3.3 V
SCAS628B – APRIL 1999 REVISED NOVEMBER 1999
PW PACKAGE
(TOP VIEW)
AGND 1
V_CC 2
1Y0 3
1Y1 4
1Y2 5
GND 6
GND 7
1Y3 8
1Y4 9
V_CC 10
G 11
FBOUT 12
24 CLK
23 AV_CC
22 V_CC
21 1Y9
20 1Y8
19 GND
18 GND
17 1Y7
16 1Y6
15 1Y5
14 V_CC
13 FBIN
description
The CDCF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDCF2510 operates at 3.3 V V_CC. It also
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50%, independent of the duty cycle at CLK. The outputs can be enabled/disabled with the control (G) input.
When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the
outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDCF2510 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDCF2510 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AV_CC to ground.
The CDCF2510 is characterized for operation from 0°C to 85°C.
For application information refer to application reports High Speed Distribution Design Techniques for
CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread
Spectrum Clocking (SSC) (literature number SCAA039).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1999, Texas Instruments Incorporated
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