CDC509 Datasheet, PDF (1/9 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC509
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
D Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs
D Separate Output Enable for Each Output
Bank
D External Feedback (FBIN) Pin Is Used to
Synchronize the Outputs to the Clock Input
D No External RC Network Required
D Operates at 3.3-V V_CC
D Packaged in Plastic 24-Pin Thin Shrink
Small-Outline Package
description
SCAS576B – JULY 1996 – REVISED JANUARY 1998
PW PACKAGE
(TOP VIEW)
AGND 1
V_CC 2
1Y0 3
1Y1 4
1Y2 5
GND 6
GND 7
1Y3 8
1Y4 9
V_CC 10
1G 11
FBOUT 12
24 CLK
23 AV_CC
22 V_CC
21 2Y0
20 2Y1
19 GND
18 GND
17 2Y2
16 2Y3
15 V_CC
14 2G
13 FBIN
The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to
precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It
is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V V_CC and is designed
to drive up to five clock loads per output.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can
be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low
state.
Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for
the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL can be bypassed for test purposes by strapping AV_CC to ground.
The CDC509 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
1G 2G CLK
OUTPUTS
1Y 2Y
(0:4) (0:3) ^FBOUT
X
X
L
L
L
L
L
L
H
L
L
H
L
H
H
L
H
H
H
L
H
H
L
H
H
H
H
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1998, Texas Instruments Incorporated
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