CDC303 Datasheet, PDF (1/7 Pages) Texas Instruments – OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER

CDC303
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
D Replaces SN74AS303
D Maximum Output Skew Between Same
Phase Outputs of 1 ns
D Maximum Pulse Skew of 1 ns
D TTL-Compatible Inputs and Outputs
D Center-Pin V_CC and GND Configurations
Minimize High-Speed Switching Noise
D Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
D OR N PACKAGE
(TOP VIEW)
Q3 ¹
Q4 ²
GND ³
GND ⁴
GND ⁵
Q5 ⁶
Q6 ⁷
Q7 ⁸
16 Q2
15 Q1
14 CLR
13 V_CC
12 V_CC
11 CLK
10 PRE
9 Q8
description
The CDC303 contains eight flip-flops designed to have low skew between outputs. The eight outputs (six
in-phase with CLK and two out-of-phase) toggle on successive CLK pulses. Preset (PRE) and clear (CLR)
inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input.
The CDC303 has output and pulse-skew parameters t_sk(o) and t_sk(p) to ensure performance as a clock driver
when a divide-by-two function is required.
The CDC303 is characterized for operation from 0°C to 70°C.
logic symbol^‡
FUNCTION TABLE
INPUTS
OUTPUTS
CLR PRE CLK Q1– Q6 Q7– Q8
L
H
X
L
H
H
L
X
H
L
L
L
X
L†
L†
H
H
↑
Q0
Q0
H
H
L
Q0
Q0
† _{This configuration does not persist when}
PRE or CLR returns to its inactive (high)
level.
10
PRE
S
11
CLK
T
14
CLR
R
15
Q1
16
Q2
1
Q3
2
Q4
6
Q5
7
Q6
8
Q7
9
Q8
‡ _{This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.}
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1995, Texas Instruments Incorporated
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