CDC111_15_15 Datasheet, PDF (1/9 Pages) Texas Instruments – 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER

CDC111
1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER
D Low-Output Skew for Clock-Distribution
Applications
D Differential Low-Voltage Pseudo-ECL
(LVPECL)-Compatible Inputs and Outputs
D Distributes Differential Clock Inputs to Nine
Differential Clock Outputs
D Output Reference Voltage, V_REF , Allows
Distribution From a Single-Ended Clock
Input
D Single-Ended LVPECL-Compatible Output
Enable
D Packaged in Plastic Chip Carrier
description
SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999
FN PACKAGE
(TOP VIEW)
Y8
Y8
Y7
V_CC0
Y7
Y6
Y6
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
Y0
Y0
Y1
V_CC0
Y1
Y2
Y2
The differential LVPECL clock-driver circuit
distributes one pair of differential LVPECL clock
inputs (CLKIN, CLKIN) to nine pairs of differential
clock (Y, Y) outputs with minimum skew for clock
distribution. It is specifically designed for driving
50-Ω transmission lines.
NC – No internal connection
When the output-enable (OE) is low, the nine differential outputs switch at the same frequency as the differential
clock inputs. When OE is high, the nine differential outputs are in static states (Y outputs are in the low state,
Y outputs are in the high state).
The V_REF output can be strapped to the CLKIN input for a single-ended CLKIN input.
The CDC111 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLKIN CLKIN OE
Yn Yn
X
X
H
L
H
L
H
L
L
H
H
L
L
H
L
L
VREF
L
H
VREF
L
VREF
L
L
VREF
H
L
L
H
H
L
H
L
L
H
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1999, Texas Instruments Incorporated
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