CD74HC390 Datasheet, PDF (1/8 Pages) Texas Instruments – High Speed CMOS Logic Dual Decade Ripple Counter

Data sheet acquired from Harris Semiconductor
SCHS185
September 1997
CD74HC390,
CD74HCT390
High Speed CMOS Logic
Dual Decade Ripple Counter
[ /Title
(CD74
HC390
,
CD74
HCT39
0)
/Sub-
ject
(High
Speed
CMOS
Features
Description
• Two BCD Decade or Bi-Quinary Counters
• One Package Can Be Configured to Divide-by-2, 4,
5,10, 20, 25, 50 or 100
• Two Master Reset Inputs to Clear Each Decade
Counter Individually
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
The Harris CD74HC390 and CD574HCT390 dual 4-bit
decade ripple counters are high-speed silicon-gate CMOS
devices and are pin compatible with low-power Schottky TTL
(LSTTL). These devices are divided into four separately
clocked sections. The counters have two divide-by-2 sec-
tions and two divide-by-5 sections. These sections are nor-
mally used in a BCD decade or bi-quinary configuration,
since they share a common master reset (nMR). If the two
master reset inputs (1MR and 2MR) are used to simulta-
neously clear all 8 bits of the counter, a number of counting
configurations are possible within one package. The sepa-
rate clock inputs (nCP0 and nCP1) of each section allow rip-
ple counter or frequency division applications of divide-by-2,
4. 5, 10, 20, 25, 50 or 100. Each section is triggered by the
High-to-Low transition of the input pulses (nCP0 and nCP1).
For BCD decade operation, the nQ0 output is connected to
the nCP1 input of the divide-by-5 section. For bi-quinary
decade operation, the nO3 output is connected to the nCP0
input and nQ₀ becomes the decade output.
The master reset inputs (1MR and 2MR) are active-High
asynchronous inputs to each decade counter which oper-
ates on the portion of the counter identified by the “1” and “2”
prefixes in the pin configuration. A High level on the nMR
input overrides the clock and sets the four outputs Low.
Ordering Information
Pinout
CD74HC390, CD74HCT390
TOP VIEW
1CP0 1
1MR 2
1Q₀ 3
1CP1 4
1Q₁ 5
1Q₂ 6
1Q₃ 7
GND 8
16 V_CC
15 2CP0
14 2MR
13 2Q0
12 2CP1
11 2Q₁
10 2Q₂
9 2Q₃
PART NUMBER TEMP. RANGE (^oC) PACKAGE
PKG.
NO.
CD74HC390E
-55 to 125
16 Ld PDIP E16.3
CD74HCT390E
-55 to 125
16 Ld PDIP E16.3
CD74HC390M
-55 to 125
16 Ld SOIC M16.15
CD74HCT390M
-55 to 125
16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
1
File Number 1838.2