CD74FCT646 Datasheet, PDF (1/8 Pages) Texas Instruments – BiCMOS FCT Interface Logic, Octal Bus Transceiver/Register, Three-State

CD74FCT646
Data sheet acquired from Harris Semiconductor
SCHS261
January 1997
Features
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BiCMOS FCT Interface Logic,
Octal Bus Transceiver/Register, Three-State
Description
• Buffered Inputs
•
Typical Propagation Delay:
T_A = 25^oC, C_L = 50pF
6.8ns
at
V_CC
=
5V,
• Noninverting
• SCR Latchup Resistant BiCMOS Process and
Circuit Design
• Speed of Bipolar FAST™/AS/S
• 64mA Output Sink Current
• Output Voltage Swing Limited to 3.7V at V_CC = 5V
• Controlled Output Edge Rates
• Input/Output Isolation to V_CC
• BiCMOS Technology with Low Quiescent Power
Ordering Information
PART NUMBER
TEMP.
RANGE (^oC) PACKAGE
PKG.
NO.
CD74FCT646EN
0 to 70 24 Ld PDIP E24.3
CD74FCT646M
0 to 70 24 Ld SOIC M24.3
CD74FCT646SM
0 to 70 24 Ld SSOP M24.209
NOTE: When ordering the suffix M and SM packages, use the entire
part number. Add the suffix 96 to obtain the variant in the tape and reel.
The CD74FCT646 three-state octal bus transceiver/register
uses a small geometry BiCMOS technology. The output
stage is a combination of bipolar and CMOS transistors that
limits the output HIGH level to two diode drops below V_CC.
This resultant lowering of output swing (0V to 3.7V)
reduces power bus ringing (a source of EMI) and minimizes
V_CC bounce and ground bounce and their effects during
simultaneous output switching. The output configuration
also enhances switching speed and is capable of sinking
64 milliamperes.
This device is a bus transceiver with D-Type flip-flops which
act as internal storage registers on the LOW to HIGH transi-
tion of either CAB or CBA clock inputs. Output Enable (OE)
and Direction (DIR) inputs control the transceiver functions.
Data present at the high impedance output can be stored in
either register or both but only one of the two buses can be
enabled as outputs at any one time. The Select controls
(SAB and SBA) can multiplex stored and transparent (real
time) data. The Direction control determines which data bus
will receive data when the Output Enable (OE) is LOW. In the
high impedance mode (Output Enable HIGH), A data can be
stored in one register and B data can be stored in the other
register. The clocks are not gated with the Direction (DIR)
and Output Enable (OE) terminals; data at the A or B termi-
nals can be clocked into the storage flip-flops at any time.
Pinout
CD74FCT646
(PDIP, SOIC, SSOP)
TOP VIEW
CAB 1
SAB 2
DIR 3
A0 4
A1 5
A2 6
A3 7
A4 8
A5 9
A6 10
A7 11
GND 12
24 V_CC
23 _CBA
22 SBA
21 OE
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1997
8-67
File Number 2393.2