CD74AC280 Datasheet, PDF (1/5 Pages) Texas Instruments – 9-Bit Odd/Even Parity Generator/Checker

Data sheet acquired from Harris Semiconductor
SCHS250
August 1998
CD74AC280,
CD74ACT280
9-Bit Odd/Even Parity Generator/Checker
Features
• Buffered Inputs
• Typical Propagation Delay
- 10ns at V_CC = 5V, T_A = 25^oC, C_L = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
Pinout
CD74AC280, CD74ACT280
(PDIP, SOIC)
TOP VIEW
I6 1
I7 2
NC 3
I8 4
∑E 5
∑O 6
GND 7
14 V_CC
13 I5
12 I4
11 I3
10 I2
9 I1
8 I0
Description
The CD74AC280 and CD74ACT280 9-bit odd/even parity
generator/checkers that utilize the Harris Advanced CMOS
Logic technology. Bothe even and odd parity outputs are
available for checking or generating parity for words up to
nine bits long. Even parity is indicated (∑Eoutput is HIGH)
when an even number of data inputs is HIGH. Odd parity is
indicated (∑O output is HIGH) when an odd number of data
inputs is HIGH. Parity checking for words larger than nine
bits can be accomplished by tying the ∑E output to any input
of an additional AC/ACT280 parity checker.
Ordering Information
PART
NUMBER
CD74AC280E
CD74ACT280E
CD74AC280M
CD74ACT280M
TEMP.
RANGE (^oC)
PACKAGE
0 to 70^oC, -40 to 85, 14 Ld PDIP
-55 to 125
0 to 70^oC, -40 to 85, 14 Ld PDIP
-55 to 125
0 to 70^oC, -40 to 85, 14 Ld SOIC
-55 to 125
0 to 70^oC, -40 to 85, 14 Ld SOIC
-55 to 125
PKG.
NO.
E14.3
E14.3
M14.15
M14.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
Functional Diagram
8
I0
9
I1
10
I2
11
I3
12
I4
13
I5
1
I6
2
I7
4
I8
5
∑ EVEN
6
∑ ODD
GND = 7
V_CC = 14
NC = 3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1998
1
File Number 1957.1