CD54HC670 Datasheet, PDF (1/14 Pages) Texas Instruments – High-Speed CMOS Logic 4x4 Register File

Data sheet acquired from Harris Semiconductor
SCHS195C
January 1998 - Revised October 2003
CD54HC670, CD74HC670,
CD74HCT670
High-Speed CMOS Logic
4x4 Register File
[ /Title
(CD74H
C670,
CD74H
CT670)
/Subject
(High-
Speed
CMOS
Logic
4x4 Reg-
ister
Features
Description
• Simultaneous and Independent Read and Write
Operations
• Expandable to 512 Words of n-Bits
• Three-State Outputs
• Organized as 4 Words x 4 Bits Wide
• Buffered Inputs
•
Typical Read Time
15pF, T_A = 25^oC
=
16ns
for
’HC670
V_CC
=
5V,
C_L
=
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
The ’HC670 and CD74HCT670 are 16-bit register files
organized as 4 words x 4 bits each. Read and write address
and enable inputs allow simultaneous writing into one location
while reading another. Four data inputs are provided to store
the 4-bit word. The write address inputs (WA0 and WA1)
determine the location of the stored word in the register.
When write enable (WE) is low the word is entered into the
address location and it remains transparent to the data. The
outputs will reflect the true form of the input data. When (WE)
is high data and address inputs are inhibited. Data acquisition
from the four registers is made possible by the read address
inputs (RA1 and RA0). The addressed word appears at the
output when the read enable (RE) is low. The output is in the
high impedance state when the (RE) is high. Outputs can be
tied together to increase the word capacity to 512 x 4 bits.
Ordering Information
PART NUMBER
TEMP. RANGE
(^oC)
PACKAGE
CD54HC670F3A
-55 to 125
16 Ld CERDIP
CD74HC670E
-55 to 125
16 Ld PDIP
CD74HC670M
-55 to 125
16 Ld SOIC
CD74HC670MT
-55 to 125
16 Ld SOIC
CD74HC670M96
-55 to 125
16 Ld SOIC
CD74HCT670E
-55 to 125
16 Ld PDIP
CD74HCT670M
-55 to 125
16 Ld SOIC
CD74HCT670MT
-55 to 125
16 Ld SOIC
CD74HCT670M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
Pinout
CD54HC670
(CERDIP)
CD74HC670, CD74HCT670
(PDIP, SOIC)
TOP VIEW
D1 1
D2 2
D3 3
RA1 4
RA0 5
Q3 6
Q2 7
GND 8
16 V_CC
15 D0
14 WA0
13 WA1
12 WE
11 RE
10 Q0
9 Q1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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