CD54HC280 Datasheet, PDF (1/9 Pages) Texas Instruments – High-Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker

Data sheet acquired from Harris Semiconductor
SCHS175D
November 1997 - Revised October 2003
CD54HC280, CD74HC280,
CD54HCT280, CD74HCT280
High-Speed CMOS Logic
9-Bit Odd/Even Parity Generator/Checker
[ /Title
(CD74
HC280
,
CD74
HCT28
0)
/Sub-
ject
(High
Speed
CMOS
Logic
9-Bit
Odd/E
ven
Parity
Features
Description
•
Typical Propagation Delay
C_L = 15pF, T_A = 25^oC
=
17ns
at
V_CC
=
5V,
• Replaces LS180 Types
• Easily Cascadable
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
The ’HC280 and ’HCT280 are 9-bit odd/even parity, generator
checker devices. Both even and odd parity outputs are
available for checking or generating parity for words up to nine
bits long. Even parity is indicated (ΣE output is high) when an
even number of data inputs is high. Odd parity is indicated
(ΣO output is high) when an odd number of data inputs is
high. Parity checking for words larger than 9 bits can be
accomplished by tying the ΣE output to any input of an
additional HC/HCT280 parity checker.
Ordering Information
PART NUMBER
TEMP. RANGE
(^oC)
PACKAGE
CD54HC280F3A
-55 to 125 14 Ld CERDIP
CD54HCT280F3A
-55 to 125 14 Ld CERDIP
CD74HC280E
-55 to 125 14 Ld PDIP
CD74HC280MT
-55 to 125 14 Ld SOIC
CD74HC280M96
-55 to 125 14 Ld SOIC
CD74HCT280E
-55 to 125 14 Ld PDIP
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
Pinout
CD54HC280, CD54HCT280
(CERDIP)
CD74HC280
(PDIP, SOIC)
CD74HCT280
(PDIP)
TOP VIEW
I6 1
I7 2
NC 3
I8 4
ΣE 5
ΣO 6
GND 7
14 V_CC
13 I5
12 I4
11 I3
10 I2
9 I1
8 I0
Functional Diagram
8
I0
9
I1
10
I2
11
I3
12
I4
13
I5
1
I6
2
I7
4
I8
5
∑ EVEN
6
∑ ODD
GND = 7
V_CC = 14
NC = 3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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