CD54HC259_08 Datasheet, PDF (1/16 Pages) Texas Instruments – High-Speed CMOS Logic 8-Bit Addressable Latch

CD54HC259, CD74HC259,
CD54HCT259, CD74HCT259
Data sheet acquired from Harris Semiconductor
SCHS173C
November 1997 - Revised October 2003
High-Speed CMOS Logic
8-Bit Addressable Latch
[ /Title
(CD74
HC259
,
CD74
HCT25
9)
/Sub-
ject
(High
Speed
CMOS
Logic
8-Bit
Addres
sable
Latch)
Features
Description
• Buffered Inputs and Outputs
• Four Operating Modes
•
Typical Propagation Delay
C_L = 15pF, T_A = 25^oC
of
15ns
at
V_CC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
The ’HC259 and ’HCT259 Addressable Latch features the
low-power consumption associated with CMOS circuitry and
has speeds comparable to low-power Schottky.
This latches three active modes and one reset mode. When
both the Latch Enable (LE) and Master Reset (MR) inputs are
low (8-line Demultiplexer mode) the output of the addressed
latch follows the Data input and all other outputs are forced
low. When both MR and LE are high (Memory Mode), all
outputs are isolated from the Data input, i.e., all latches hold
the last data presented before the LE transition from low to
high. A condition of LE low and MR high (Addressable Latch
mode) allows the addressed latch’s output to follow the data
input; all other latches are unaffected. The Reset mode (all
outputs low) results when LE is high and MR is low.
Ordering Information
PART NUMBER
CD54HC259F3A
CD54HCT259F3A
CD74HC259E
CD74HC259M
TEMP. RANGE
(^oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
CD74HC259MT
-55 to 125
16 Ld SOIC
CD74HC259M96
-55 to 125
16 Ld SOIC
CD74HCT259E
-55 to 125
16 Ld PDIP
CD74HCT259M
-55 to 125
16 Ld SOIC
CD74HCT259MT
-55 to 125
16 Ld SOIC
CD74HCT259M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1