CD54HC221_07 Datasheet, PDF (1/22 Pages) Texas Instruments – High-Speed CMOS Logic Dual Monostable Multivibrator with Reset

Data sheet acquired from Harris Semiconductor
SCHS166F
November 1997 - Revised October 2003
CD54HC221, CD74HC221,
CD74HCT221
High-Speed CMOS Logic
Dual Monostable Multivibrator with Reset
[ /Title
(CD74
HC221
,
CD74
HCT22
1)
/Sub-
ject
(High
Speed
CMOS
Logic
Dual
Monos
table
Multi-
Features
Description
• Overriding RESET Terminates Output Pulse
• Triggering from the Leading or Trailing Edge
• Q and Q Buffered Outputs
• Separate Resets
• Wide Range of Output-Pulse Widths
• Schmitt Trigger on B Inputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
Pinout
CD54HC221
(CERDIP)
CD74HC221
(PDIP, SOIC, SOP, TSSOP)
CD74HCT221
(PDIP, SOIC)
TOP VIEW
1A 1
1B 2
1R 3
1Q 4
2Q 5
2C_X 6
2C_XR_X 7
GND 8
16 V_CC
15 1C_XR_X
14 1C_X
13 1Q
12 2Q
11 2R
10 2B
9 2A
The ’HC221 and CD74HCT221 are dual monostable
multivibrators with reset. An external resistor (R_X) and an
external capacitor (C_X) control the timing and the accuracy
for the circuit. Adjustment of R_X and C_X provides a wide
range of output pulse widths from the Q and Q terminals.
Pulse triggering on the B input occurs at a particular voltage
level and is not related to the rise and fall time of the trigger
pulse.
Once triggered, the outputs are independent of further trigger
inputs on A and B. The output pulse can be terminated by a
LOW level on the Reset (R) pin. Trailing Edge triggering (A)
and leading-edge-triggering (B) inputs are provided for
triggering from either edge of the input pulse. On power up,
the IC is reset. If either Mono is not used each input (on the
unused device) must be terminated either high or low.
The minimum value of external resistance, R_X, is typically 500Ω.
The minimum value of external capacitance, C_X, is 0pF. The
calculation for the pulse width is t_W = 0.7 R_XC_X at V_CC = 4.5V.
Ordering Information
PART NUMBER TEMP. RANGE (^oC)
PACKAGE
CD54HC221F3A
-55 to 125
16 Ld CERDIP
CD74HC221E
-55 to 125
16 Ld PDIP
CD74HC221M
-55 to 125
16 Ld SOIC
CD74HC221MT
-55 to 125
16 Ld SOIC
CD74HC221M96
-55 to 125
16 Ld SOIC
CD74HC221NSR
-55 to 125
16 Ld SOP
CD74HC221PW
-55 to 125
16 Ld TSSOP
CD74HC221PWR
-55 to 125
16 Ld TSSOP
CD74HC221PWT
-55 to 125
16 Ld TSSOP
CD74HCT221E
-55 to 125
16 Ld PDIP
CD74HCT221M
-55 to 125
16 Ld SOIC
CD74HCT221MT
-55 to 125
16 Ld SOIC
CD74HCT221M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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