CD54HC04F3A Datasheet, PDF (1/17 Pages) Texas Instruments – High-Speed CMOS Logic Hex Inverter

Data sheet acquired from Harris Semiconductor
SCHS117E
August 1997 - Revised June 2004
CD54HC04, CD74HC04,
CD54HCT04, CD74HCT04
High-Speed CMOS Logic Hex Inverter
[ /Title
(CD54H
C04,
CD54H
CT04,
CD74H
C04,
CD74H
CT04)
/Subject
(High
Speed
Features
Description
• Buffered Inputs
•
Typical Propagation Delay:
C_L = 15pF, T_A = 25^oC
6ns
at
V_CC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2-V to 6-V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5-V to 5.5-V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
The CD54HC04, CD54HCT04, CD74HC04 and
CD74HCT04 logic gates utilize silicon-gate CMOS
technology to achieve operating speeds similar to LSTTL
gates, with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The 74HCT logic family functionally is pin
compatible with the standard 74LS logic family.
Ordering Information
PART NUMBER
CD54HC04F3A
CD54HCT04F3A
CD74HC04E
CD74HC04M
CD74HC04MT
CD74HC04M96
CD74HCT04E
CD74HCT04M
TEMP. RANGE
(^oC)
PACKAGE
-55 to 125
14 Ld CERDIP
-55 to 125
14 Ld CERDIP
-55 to 125
14 Ld PDIP
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld PDIP
-55 to 125
14 Ld SOIC
CD74HCT04MT
-55 to 125
14 Ld SOIC
CD74HCT04M96
-55 to 125
14 Ld SOIC
CD74HCT04PWR
-55 to 125
14 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes
96 and R denote tape and reel. The suffix T denotes a
small-quantity reel of 250.
Pinout
CD54HC04, CD54HCT04 (CERDIP)
CD74HC04 (PDIP, SOIC)
CD74HCT04 (PDIP, SOIC, TSSOP)
TOP VIEW
1A 1
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND 7
14 V_CC
13 6A
12 6Y
11 5A
10 5Y
9 4A
8 4Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
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