CD54ACT161 Datasheet, PDF (1/14 Pages) Texas Instruments – 4-BIT SYNCHRONOUS BINARY COUNTERS

CD54ACT161, CD74ACT161
4-BIT SYNCHRONOUS BINARY COUNTERS
D Inputs Are TTL-Voltage Compatible
D Internal Look-Ahead for Fast Counting
D Carry Output for n-Bit Cascading
D Synchronous Counting
D Synchronously Programmable
D SCR-Latchup-Resistant CMOS Process and
Circuit Design
D Exceeds 2-kV ESD Protection per
MIL-STD-883, Method 3015
description/ordering information
SCHS298B – APRIL 2000 – REVISED MARCH 2003
CD54ACT161 . . . F PACKAGE
CD74ACT161 . . . E OR M PACKAGE
(TOP VIEW)
CLR 1
CLK 2
A3
B4
C5
D6
ENP 7
GND 8
16 V_CC
15 RCO
14 Q_A
13 Q_B
12 Q_C
11 Q_D
10 ENT
9 LOAD
The ’ACT161 devices are 4-bit binary counters. These synchronous, presettable counters feature an internal
carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having
all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed
by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output
counting spikes that normally are associated with synchronous (ripple-clock) counters. A buffered clock (CLK)
input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
These devices are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.
Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes
the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low,
regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15, with Q_A high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
TA
–55°C to 125°C
ORDERING INFORMATION
PACKAGE†
ORDERABLE
PART NUMBER
PDIP – E Tube
CD74ACT161E
Tube
SOIC – M
Tape and reel
CD74ACT161M
CD74ACT161M96
CDIP – F Tube
CD54ACT161F3A
TOP-SIDE
MARKING
CD74ACT161E
ACT161M
CD54ACT161F3A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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