CD54AC280_07 Datasheet, PDF (1/12 Pages) Texas Instruments – 9-Bit Odd/Even Parity Generator/Checker

Data sheet acquired from Harris Semiconductor
SCHS250A
August 1998 - Revised May 2000
CD54/74AC280,
CD54/74ACT280
9-Bit Odd/Even Parity Generator/Checker
Features
• Buffered Inputs
• Typical Propagation Delay
- 10ns at V_CC = 5V, T_A = 25^oC, C_L = 50pF
• Exceeds 2kV ESD Protection per MIL-STD-883,
Method 3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
Description
The ’AC280 and ’ACT280 are 9-bit odd/even parity genera-
tor/checkers that utilize Advanced CMOS Logic technology.
Both even and odd parity outputs are available for checking
or generating parity for words up to nine bits long. Even par-
ity is indicated (∑E output is HIGH) when an even number of
data inputs is HIGH. Odd parity is indicated (∑O output is
HIGH) when an odd number of data inputs is HIGH. Parity
checking for words larger than nine bits can be accom-
plished by tying the ∑E output to any input of an additional
’AC280, ’ACT280 parity checker.
Ordering Information
PART
NUMBER
TEMP.
RANGE (^oC)
PACKAGE
CD54AC280F3A
CD74AC280E
CD74AC280M
-55 to 125
0 to 70^oC, -40 to 85,
-55 to 125
0 to 70^oC, -40 to 85,
-55 to 125
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
CD54ACT280F3A
CD74ACT280E
CD74ACT280M
-55 to 125
0 to 70^oC, -40 to 85,
-55 to 125
0 to 70^oC, -40 to 85,
-55 to 125
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local TI sales office or cus-
tomer service for ordering information.
Pinout
CD54AC280, CD54ACT280
(CERDIP)
CD74AC280, CD74ACT280
(PDIP, SOIC)
TOP VIEW
I6 1
I7 2
NC 3
I8 4
∑E 5
∑O 6
GND 7
14 V_CC
13 I5
12 I4
11 I3
10 I2
9 I1
8 I0
Functional Diagram
8
I0
9
I1
10
I2
11
I3
12
I4
13
I5
1
I6
2
I7
4
I8
5
∑ EVEN
6
∑ ODD
GND = 7
V_CC = 14
NC = 3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © 2000, Texas Instruments Incorporated
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