CD54AC109 Datasheet, PDF (1/12 Pages) Intersil Corporation – Dual J-K Flip-Flop with Set and Reset

CD54AC109, CD74AC109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS326 – JANUARY 2003
D AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply Voltage
D Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D Balanced Propagation Delays
D ±24-mA Output Drive Current
– Fanout to 15 F Devices
D SCR-Latchup-Resistant CMOS Process and
Circuit Design
D Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
CD54AC109 . . . F PACKAGE
CD74AC109 . . . E OR M PACKAGE
(TOP VIEW)
1CLR 1
1J 2
1K 3
1CLK 4
1PRE 5
1Q 6
1Q 7
GND 8
16 V_CC
15 2CLR
14 2J
13 2K
12 2CLK
11 2PRE
10 2Q
9 2Q
description/ordering information
The ’AC109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to
the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and
is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs
can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E
Tube
CD74AC109E
CD74AC109E
–55°C to 125°C SOIC – M
Tape and reel CD74AC109M96
AC109M
CDIP – F
Tube
CD54AC109F3A
CD54AC109F3A
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines}
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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