CD5474FCT373 Datasheet, PDF (1/2 Pages) Texas Instruments – FCT Interface Logic Octal Transparent Latch, Three-State

Data sheet acquired from Harris Semiconductor
SCHS272
February 1996
CD54/74FCT373,
CD54/74FCT373AT,
CD54/74FCT533
FCT Interface Logic
Octal Transparent Latch, Three-State
Features
Description
• CD54/74FCT373, CD54/74FCT373AT - Non-Inverting
• CD54/74FCT533 - Inverting
• Buffered inputs
• Typical Propagation Delay: 3.9ns at VCC = 5V,
TA = +25^oC, CL = 50pF (FCT373AT)
• SCR-Latchup-Resistant BiCMOS Process and Circuit
Design
• FCTXXX Types - Speed of Bipolar FAST®/AS/S;
FCTXXXAT Types - 30% Faster than FAST/AS/S with
Significantly Reduced Power Consumption
• 48mA to 32mA Output Sink Current (Commercial/
Extended Industrial)
• Output Voltage Swing Limited to 3.7V at VCC = 5V
• Controlled Output-Edge Rates
• Input/Output Isolation to VCC
• BiCMOS Technology with Low Quiescent Power
The CD54/74FCT373, 373AT, and 533 octal transparent
latches use a small-geometry BiCMOS technology. The output
stage is a combination of bipolar and CMOS transistors that
limits the output-HIGH level to two diode drops below VCC. This
resultant lowering of output swing (0V to 3.7V) reduces power
bus ringing (a source of EMI) and minimizes VCC bounce and
ground bounce and their effects during simultaneous output
switching. The output configuration also enhances switching
speed and is capable of sinking 32mA to 48mA.
The CD54/74FCT373, 373AT, and 533 outputs are transpar-
ent to the inputs when the Latch Enable (LE) is HIGH. When
the Latch Enable (LE) goes LOW, the data is latched. The
Output Enable (OE) controls the three-state outputs. When
the Output Enable (OE) is HIGH, the outputs are in the high-
impedance state. The latch operation is independent of the
state of the Output Enable.
Ordering Information
PART NUMBER
TEMP. RANGE (^oC) PACKAGE
CD54/74FCT373E
-55 to 125, 0 to 70 20 Ld PDIP
CD54/74FCT373ATE
-55 to 125, 0 to 70 20 Ld PDIP
CD54/74FCT533E
-55 to 125, 0 to 70 20 Ld PDIP
CD54/74FCT373M
-55 to 125, 0 to 70 20 Ld SOIC
CD54/74FCT373ATM -55 to 125, 0 to 70 20 Ld SOIC
CD54/74FCT533M
-55 to 125, 0 to 70 20 Ld SOIC
CD54/74FCT373SM
-55 to 125, 0 to 70 20 Ld SSOP
CD54/74FCT533SM
-55 to 125, 0 to 70 20 Ld SSOP
CD54FCT373H
-55 to 125
CD54FCT533H
-55 to 125
Functional Diagram
D0 ³
D1 ⁴
D2 ⁷
D3 ⁸
D4 ¹³
D5 ¹⁴
D6 ¹⁷
D7 ¹⁸
373 533
2 _Q0
Q0
5 _Q1
Q1
6 _Q2
Q2
9 _Q3
Q3
12 _Q4
Q4
15 _Q5
Q5
16 _Q6
Q6
19 _Q7
Q7
11 1
LE
OE
TRUTH TABLE
OUTPUT LATCH
ENABLE ENABLE
DATA
373, 373AT
533
OUTPUT OUTPUT
L
H
H
H
L
L
H
L
L
H
L
L
I
L
H
L
L
h
H
L
H
X
X
Z
Z
H = HIGH voltage level.
L = LOW voltage level.
X = Irrelevant.
Z = HIGH Impedance.
I = LOW voltage level one setup time
prior to the high-to-low latch enable
transition.
h = HIGH voltage level one setup time
prior to the high-to-low latch enable
transition.
FAST® is a registered trademark of Fairchild Semiconductor Corporation.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996
1
File Number 2230.2