CD4541B_101 Datasheet, PDF (1/17 Pages) Texas Instruments – CMOS Programmable Timer High Voltage Types (20V Rating)

CD4541B
Data sheet acquired from Harris Semiconductor
SCHS085E – Revised September 2003
CMOS Programmable Timer
High Voltage Types (20V Rating)
[ /Title
(CD45
41B)
/Sub-
ject
(CMO
S Pro-
gram-
mable
Timer
High
Volt-
age
Types
(20V
Rat-
ing))
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
CD400
0,
metal
gate,
CMOS
, pdip,
cerdip,
mil,
mili-
tary,
mil
Features
• Low Symmetrical Output Resistance, Typically 100Ω
at V_DD = 15V
• Built-In Low-Power RC Oscillator
• Oscillator Frequency Range . . . . . . . . . . DC to 100kHz
• External Clock (Applied to Pin 3) can be Used Instead
of Oscillator
• Operates as 2^N Frequency Divider or as a Single-
Transition Timer
• Q/Q Select Provides Output Logic Level Flexibility
• AUTO or MASTER RESET Disables Oscillator During
Reset to Reduce Power Dissipation
• Operates With Very Slow Clock Rise and Fall Times
• Capable of Driving Six Low Power TTL Loads, Three
Low-Power Schottky Loads, or Six HTL Loads Over
the Rated Temperature Range
• Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V, and 15V Parametric Ratings
• Meets All Requirements of JEDEC Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series
CMOS Devices”
Description
CD4541B programmable timer consists of a 16-stage binary
counter, an oscillator that is controlled by external R-C compo-
nents (2 resistors and a capacitor), an automatic power-on
reset circuit, and output control logic. The counter increments
on positive-edge clock transitions and can also be reset via the
MASTER RESET input.
Pinout
CD4541B
(CERDIP, PDIP, SOIC, SOP, TSSOP)
TOP VIEW
R_TC 1
C_TC 2
R_S 3
NC 4
AUTO RESET 5
MASTER RESET 6
V_SS 7
14 V_DD
13 B
12 A
11 NC
10 MODE
9 Q/Q SELECT
8 OUTPUT
The output from this timer is the Q or Q output from the 8th,
10th, 13th, or 16th counter stage. The desired stage is chosen
using time-select inputs A and B (see Frequency Select Table).
The output is available in either of two modes selectable via the
MODE input, pin 10 (see Truth Table). When this MODE input is
a logic “1”, the output will be a continuous square wave having
a frequency equal to the oscillator frequency divided by 2^N.
With the MODE input set to logic “0” and after a MASTER
RESET is initiated, the output (assuming Q output has been
selected) changes from a low to a high state after 2^N-1 counts
and remains in that state until another MASTER RESET pulse
is applied or the MODE input is set to a logic “1”.
Timing is initialized by setting the AUTO RESET input (pin 5) to
logic “0” and turning power on. If pin 5 is set to logic “1”, the
AUTO RESET circuit is disabled and counting will not start until
after a positive MASTER RESET pulse is applied and returns
to a low level. The AUTO RESET consumes an appreciable
amount of power and should not be used if low-power operation
is desired. For reliable automatic power-on reset, V_DD should
be greater than 5V.
The RC oscillator, shown in Figure 2, oscillates with a
frequency determined by the RC network and is calculated
using:
f = -₂---_.--₃-----_R-----_T-¹---_C----_C----_T----_C--
Where f is between 1kHz
and 100kHz
and R_S ≥ 10kΩ and ≈ 2R_TC
Ordering Information
PART NUMBER
TEMP. RANGE
(^oC)
PACKAGE
CD4541BF3A
-55 to 125 14 Ld CERDIP
CD4541BE
-55 to 125 14 Ld PDIP
CD4541BM
-55 to 125 14 Ld SOIC
CD4541BMT
-55 to 125 14 Ld SOIC
CD4541BM96
-55 to 125 14 Ld SOIC
CD4541BNSR
-55 to 125 14 Ld SOP
CD4541BPW
-55 to 125 14 Ld TSSOP
CD4541BPWR
-55 to 125 14 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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