74ACT11027 Datasheet, PDF (1/5 Pages) Texas Instruments – TRIPLE 3-INPUT POSITIVE-NOR GATES

• Inputs Are TTL-Voltage Compatible
• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin V_CC and GND Configurations
Minimize High-Speed Switching Noise
• EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These devices contain three independent 3-input
NOR gates. They perform the Boolean functions
Y = A + B + C or Y = ASBSC in positive logic.
The 54ACT11027 is characterized for operation
over the full military temperature range of – 55°C
to 125°C. The 74ACT11027 is characterized for
operation from – 40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
A
B
C
OUTPUT
Y
H
X
X
L
X
H
X
L
X
X
H
L
L
L
L
H
logic symbol^†
1A ¹
≥1
1B ¹⁶
2 _1Y
1C ¹⁵
2A ¹⁴
2B ¹¹
3 _2Y
2C ¹⁰
3A ⁹
3B ⁸
6 _3Y
3C ⁷
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984}
and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
54ACT11027, 74ACT11027
TRIPLE 3-INPUT POSITIVE-NOR GATES
SCAS020A – D2957, JULY 1987 – REVISED APRIL 1993
54ACT11027 . . . J PACKAGE
74ACT11027 . . . D OR N PACKAGE
(TOP VIEW)
1A 1
1Y 2
2Y 3
GND 4
GND 5
3Y 6
3C 7
3B 8
16 1B
15 1C
14 2A
13 V_CC
12 V_CC
11 2B
10 2C
9 3A
54ACT11027 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
1C 4
18 2C
1B 5
17 3A
NC 6
16 NC
1A 7
15 3B
1Y 8
14 3C
9 10 11 12 13
NC – No internal connection
logic diagram (positive logic)
1A
1B
1
16
15
1C
2
1Y
2A
2B
2C
14
11
10
3
2Y
3A
3B
3C
9
8
7
6
3Y
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1993, Texas Instruments Incorporated
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