74ACT11000DR Datasheet, PDF (1/6 Pages) Texas Instruments – QUADRUPLE 2-INPUT POSITIVE-NAND GATES

54ACT11000, 74ACT11000
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
• Inputs Are TTL-Voltage Compatible
• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin V_CC and GND Configurations
Minimize High-Speed Switching Noise
• EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and
Ceramic 300-mil DIPs
description
These devices contain four independent 2-input
NAND gates. They perform the Boolean functions
Y = ASB or Y = A + B in positive logic.
The 54ACT11000 is characterized for operation
over the full military temperature range of – 55°C
to 125°C. The 74ACT11000 is characterized for
operation from – 40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
A
B
OUTPUT
Y
H
H
L
L
X
H
X
L
H
SCAS002A – D2957, JUNE 1987 – REVISED APRIL 1993
54ACT11000 . . . J PACKAGE
74ACT11000 . . . D OR N PACKAGE
(TOP VIEW)
1A 1
1Y 2
2Y 3
GND 4
GND 5
3Y 6
4Y 7
4B 8
16 1B
15 2A
14 2B
13 V_CC
12 V_CC
11 3A
10 3B
9 4A
54ACT11000 . . . FK PACKAGE
(TOP VIEW)
2A
3 2 1 20 19
4
18
3B
1B ₅
17 ^4A
NC 6
16 NC
1A 7
15 4B
1Y 8
14 4Y
9 10 11 12 13
NC – No internal connection
logic symbol^†
1
1A
&
16
1B
15
2A
14
2B
11
3A
10
3B
9
4A
8
4B
2
1Y
3
2Y
6
3Y
7
4Y
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984}
and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
1A
1Y
1B
2A
2Y
2B
3A
3Y
3B
4A
4Y
4B
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1993, Texas Instruments Incorporated
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