74AC11286 Datasheet, PDF (1/7 Pages) Texas Instruments – 9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS

• Generates Either Odd or Even Parity for
Nine Data Lines
• Cascadable for n-Bits Parity
• Direct Bus Connection for Parity
Generation or for Checking by Using the
Parity I/O Port
• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin V_CC and GND Configurations
Minimize High-Speed Switching Noise
t • EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
• 500-mA Typical Latch-Up Immunity
at 125°C
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
74AC11286
9-BIT PARITY GENERATOR/CHECKER
WITH BUS DRIVER PARITY I/O PORTS
SCAS068A – AUGUST 1988 – REVISED APRIL 1993
D OR N PACKAGE
(TOP VIEW)
B1
A2
PARITY I/O 3
GND 4
PARITY ERROR 5
XMIT 6
I7
14 C
13 D
12 E
11 V_CC
10 F
9G
8H
description
The 74AC11286 universal 9-bit parity generator/checker features a local output for parity checking and a
bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by
cascading.
The XMIT control input is implemented specifically to accommodate cascading. When the XMIT is low, the parity
tree is disabled and the PARITY ERROR output will remain at a high logic level regardless of the input levels.
When XMIT is high, the parity tree is enabled. The PARITY ERROR output will indicate a parity error when either
an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd
number of inputs are high and PARITY I/O is forced to a high logic level.
The I/O control circuitry was designed so that the I/O port will remain in the high-impedance state during power
up or power down to prevent bus glitches.
The 74AC11286 is characterized for operation from – 40°C to 85°C.
FUNCTION TABLE
NUMBER OF INPUTS
(A THRU I) THAT
ARE HIGH
XMIT
INPUT
PARITY
I/O
PARITY
ERROR
OUTPUT
0, 2, 4, 6, 8
l
H
H
1, 3, 5, 7, 9
l
L
H
0, 2, 4, 6, 8
h
h
H
h
l
L
1, 3, 5, 7, 9
h
h
L
h
l
H
h — high input level
H — high output level
l — low input level
L — low output level
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1993, Texas Instruments Incorporated
2–1