74AC11162 Datasheet, PDF (1/10 Pages) Texas Instruments – SYNCHRONOUS 4-BIT DECADE COUNTER

74AC11162
SYNCHRONOUS 4-BIT DECADE COUNTER
• Internal Look-Ahead Circuitry for Fast
Counting
• Carry Output for N-Bit Cascading
• Fully Synchronous Operation for Counting
• Synchronously Programmable
• Flow-Through Architecture Optimizes PCB
Layout
• Center-Pin V_CC and GND Configurations
Minimize High-Speed Switching Noise
• EPIC ™ (Enhanced-Performance Implanted
CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
SCAS381 – D3199, AUGUST 1988 – REVISED APRIL 1993
DW OR N PACKAGE
(TOP VIEW)
RCO ₁
Q_{A 2}
Q_B 3
GND 4
GND 5
GND 6
GND 7
Q_C 8
Q_D 9
LOAD 10
20 ^CLR
19 ^CLK
18 A
17 B
16 V_CC
15 V_CC
14 C
13 D
12 ENP
11 ENT
description
This synchronous, presettable 4-bit decade counter features an internal carry look-ahead circuitry for
application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each other when so instructed by the count-enable
inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally
associated with asynchronous (ripple-clock) counters; however, counting spikes may occur on the ripple-carry
(RCO) output. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the
clock-input waveform.
These counters are fully programmable in that they may be preset to any number between 0 and 9. As presetting
is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to
agree with the setup data after the next clock pulse regardless of the levels of the enable inputs.
If one of these decade counters is preset to a number between 10 and 15 or assumes such an invalid state when
power is applied, it progresses to the normal sequence within two counts as shown in the state diagram.
The clear function for the 74AC11162 is synchronous, and a low level at the clear (CLR) input drives all four of
the flip-flop outputs low after the next low-to-high transition of the clock regardless of the levels on the
count-enable (ENP and ENT) inputs. This synchronous clear allows the count length to be modified easily by
decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding
is connected to the clear input to synchronously clear the counter to 0000 (LLLL on the Q outputs).
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1993, Texas Instruments Incorporated
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