54ACT11109 Datasheet, PDF (1/5 Pages) Texas Instruments – DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

54ACT11109, 74ACT11109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993
• Inputs Are TTL-Voltage Compatible
• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin V_CC and GND Configurations
Minimize High-Speed Switching Noise
• EPIC™ (Enhanced-Performance Implanted
CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity
at 125°C
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and
Ceramic 300-mil DIPs
description
54ACT11109 . . . J PACKAGE
74ACT11109 . . . D OR N PACKAGE
(TOP VIEW)
1PRE 1
1Q 2
1Q 3
GND 4
2Q 5
2Q 6
2PRE 7
2CLK 8
16 ^1CLK
15 ^1K
14 ^1J
13 1CLR
12 V_CC
11 2CLR
10 2J
9 2K
54ACT11109 . . . FK PACKAGE
(TOP VIEW)
These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (1PRE or 2PRE) or clear (1CLR or
2CLR) input sets or resets the outputs regardless
of the levels of the other inputs. When PRE and
CLR are inactive (high), data at the J and K inputs
meeting the setup time requirements are
transferred to the outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at
a voltage level and is not directly related to the rise
time of the clock pulse. Following the hold-time
interval, data at the J and K inputs may be
changed without affecting the levels at the
outputs. These versatile flip-flops can perform as
toggle flip-flops by grounding K and tying J high.
They also can perform as D-type flip-flops if J and
K are tied together.
1K
1CLK
NC
1PRE
1Q
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2J
2K
NC
2CLK
2PRE
NC – No internal connection
The 54ACT11109 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
74ACT11109 is characterized for operation from – 40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE CLR CLK J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H†
H†
H
H
↑
L
L
L
H
H
H
↑
H
L
Toggle
H
H
↑
L
H
Q0 Q0
H
H
↑
H
H
H
L
H
H
L
X
X
Q0 Q0
† _{This configuration is nonstable; that is, it will not persist when}
either PRE or CLR returns to the inactive (high) level.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1993, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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