54ACT11010 Datasheet, PDF (1/5 Pages) Texas Instruments – TRIPLE 3-INPUT POSITIVE-NAND GATES

54ACT11010, 74ACT11010
TRIPLE 3-INPUT POSITIVE-NAND GATES
• Inputs Are TTL-Voltage Compatible
• Flow-Through Architecture to Optimize
PCB Layout
• Center-Pin V_CC and GND Configurations
Minimize High-Speed Switching Noise
• EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
• 500-mA Typical Latch-Up Immunity
at 125°C
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These devices contain three independent 3-input
NAND gates. They perform the Boolean functions
Y = ASBSC or Y = A + B + C in positive logic.
The 54ACT11010 is characterized for operation
over the full military temperature range of – 55°C
to 125°C. The 74ACT11010 is characterized for
operation from – 40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
ABC
OUTPUT
Y
HHH
L
LXX
H
XLX
H
XXL
H
logic symbol^†
1
1A
&
16
1B
15
1C
14
2A
11
2B
10
2C
9
3A
8
3B
7
3C
2
1Y
3
2Y
6
3Y
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984}
and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SCAS018A – D2957, JULY 1987 – REVISED APRIL 1993
54ACT11010 . . . J PACKAGE
74ACT11010 . . . D OR N PACKAGE
(TOP VIEW)
1A 1
1Y 2
2Y 3
GND 4
GND 5
3Y 6
3C 7
3B 8
16 1B
15 1C
14 2A
13 V_CC
12 V_CC
11 2B
10 2C
9 3A
54ACT11010 . . . FK PACKAGE
(TOP VIEW)
1C
3 2 1 20 19
4
18
2C
1B ₅
17 ^3A
NC 6
16 NC
1A 7
15 3B
1Y 8
14 3C
9 10 11 12 13
NC – No internal connection
logic diagram (positive logic)
1
1A
1B
16
1C
15
2
1Y
2A
2B
14
11
2C
10
3 _2Y
3A
9
3B
8
3C
7
6 _3Y
Copyright © 1993, Texas Instruments Incorporated
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