THC63LVDR84C Datasheet, PDF (8/16 Pages) THine Electronics, Inc. – 24bit Color LVDS Receiver (Rising Edge Strobe Output)

THC63LVDR84C_Rev.1.20_E
Switching Characteristics
Over recommended operating supply and temperature range unless otherwise specified
Symbol
Parameter
Min
Typ*
Max
Unit
tRCP RCLK and CLKOUT Transition Time
tRCH LVCMOS CLKOUT High Time
tRCL LVCMOS CLKOUT Low Time
tRCD RCLK IN to CLKOUT Delay
tRS
LVCMOS Data Setup to CLKOUT
tRH LVCMOS Data Hold from CLKOUT
8.92
T
125
ns
-
T/2
-
ns
-
T/2
-
ns
-
(3/14+3)×T
-
ns
0.35×T - 0.3
-
-
ns
0.45×T - 1.6
-
-
ns
tTLH LVCMOS Low to High Transition Time
tTHL LVCMOS High to Low Transition Time
tSK
LVDS Receiver Skew Margin
PCLK=65MHz
PCLK=112MHz
-
-
-0.55
-0.25
0.7
1.0
ns
0.7
1.0
ns
-
-
0.55
0.25
ns
tRIP1 LVDS Input Data Position0
- tSK
tRIP0 LVDS Input Data Position1
T/7- tSK
tRIP6 LVDS Input Data Position2
2T/7- tSK
tRIP5 LVDS Input Data Position3
3T/7- tSK
tRIP4 LVDS Input Data Position4
4T/7- tSK
tRIP3 LVDS Input Data Position5
5T/7- tSK
tRIP2 LVDS Input Data Position6
6T/7- tSK
tRPLL Phase Lock Loop Set
-
*Typ values are at the conditions of VCC33=3.3V and Ta = +25ºC
0.0
T/7
2T/7
3T/7
4T/7
5T/7
6T/7
-
+ tSK
ns
T/7+ tSK
ns
2T/7+ tSK
ns
3T/7+ tSK
ns
4T/7+ tSK
ns
5T/7+ tSK
ns
6T/7+ tSK
ns
10.0
ms
Table 8. LVCMOS & LVDS Receiver AC Specifications
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