THC63LVDM87_15 Datasheet, PDF (8/13 Pages) THine Electronics, Inc. – LOW POWER / SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER

THC63LVDM87_Rev.1.00_E
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
t_TCP
t_TCH
t_TCL
t_TCD
t_TS
t_TH
t_LVT
t_TOP1
Parameter
CLK IN Period
CLK IN High Time
CLK IN Low Time
CLK IN to TCLK+/- Delay (Fig4)
TTL Data Setup to CLK IN
TTL Data Hold from CLK IN
LVDS Transition Time
Output Data Position0 (T=6.25ns~15ns)
Min.
6.25
0.35T
0.35T
5T+3.1
0.8
0.8
-0.15
Typ.
T
0.5T
0.5T
0.6
0.0
Max.
125
0.65T
0.65T
5T+8
1.5
+0.15
Units
ns
ns
ns
ns
ns
ns
ns
ns
t_TOP0 Output Data Position1 (T=6.25ns~15ns)
T--- _{– 0.15}
7
T---
T--- _{+ 0.15}
ns
7
7
t_TOP6 Output Data Position2 (T=6.25ns~15ns)
2T--- – 0.15
7
2 ^T---
2T--- + 0.15
ns
7
7
t_TOP5 Output Data Position3 (T=6.25ns~15ns)
3
T---
7
–
0.15
3 ^T---
3T--- + 0.15
ns
7
7
t_TOP4 Output Data Position4 (T=6.25ns~15ns)
t_TOP3 Output Data Position5 (T=6.25ns~15ns)
t_TOP2
t_TPLL
Output Data Position6 (T=6.25ns~15ns)
Phase Lock Loop Set
4
T---
7
–
0.15
5T--- – 0.15
7
6T--- – 0.15
7
4 ^T---
4T--- + 0.15
ns
7
7
5 ^T---
5T--- + 0.15
ns
7
7
6 ^T---
6T--- + 0.15
ns
7
7
10.0
ms
AC Timing Diagrams
LVDS Output
V_diff=(TA+)-(TA-)
TA+
V_diff
5pF _100Ω
TA-
LVDS Output Load
80%
20%
t_LVT
80%
20%
t_LVT
Fig3. LVDS Output Load and Transition Time
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THine Electronics, Inc.